Datasheet

PIC18F45J10 FAMILY
DS39682E-page 322 © 2009 Microchip Technology Inc.
FIGURE 24-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 24-7: BROWN-OUT RESET TIMING
TABLE 24-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
2.8 4.1 5.4 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 46.2 66 85.8 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—μs
38 T
CSD CPU Start-up Time — 200 — μs
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 24-3 for load conditions.
VDD
BVDD
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
Reference Voltage
Voltage Stable