Datasheet

PIC18F45J10 FAMILY
DS39682E-page 216 © 2009 Microchip Technology Inc.
REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (V
REF- source)
1 =V
REF- (AN2)
0 =V
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 =V
REF+ (AN3)
0 =V
DD
bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:
A = Analog input D = Digital I/O
Note 1: AN5 through AN7 are available only on 40/44-pin devices.
PCFG<3:0>
AN12 AN11 AN10 AN9 AN8 AN7
(1)
AN6
(1)
AN5
(1)
AN4 AN3 AN2 AN1 AN0
0000 A A AAAAAAAAAAA
0001 A A AAAAAAAAAAA
0010 A A AAAAAAAAAAA
0011 D A AAAAAAAAAAA
0100 D DAAAAAAAAAAA
0101 D DDAAAAAAAAAA
0110 D DDDAAAAAAAAA
0111 DDDDDAAAAAAAA
1000 D D DDDDAAAAAAA
1001 D D DDDDDAAAAAA
1010 D D DDDDDDAAAAA
1011 D D DDDDDDDAAAA
1100 D D DDDDDDDDAAA
1101 D D DDDDDDDDDAA
1110 D D DDDDDDDDDDA
1111 D D DDDDDDDDDDD