Datasheet

PIC18F45J10 FAMILY
DS39682E-page 210 © 2009 Microchip Technology Inc.
FIGURE 17-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49
TXREG EUSART Transmit Register 49
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 49
BAUDCON ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 49
SPBRGH EUSART Baud Rate Generator Register High Byte 49
SPBRG EUSART Baud Rate Generator Register Low Byte 49
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6 bit 7
TXEN bit