Datasheet

PIC18F45J10 FAMILY
DS39682E-page 158 © 2009 Microchip Technology Inc.
TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49
PIR3 SSP2IF
BCL2IF — — — — — —49
PIE3 SSP2IE BCL2IE — — — — — —49
IPR3 SSP2IP BCL2IP — — — — — —49
TRISA
— — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 50
TRISD
(1)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 50
SSP1BUF MSSP1 Receive Buffer/Transmit Register 48
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 48
SSP1STAT SMP CKE
D/A P S R/W UA BF 48
SSP2BUF MSSP2 Receive Buffer/Transmit Register 50
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50
SSP2STAT SMP CKE
D/A P S R/W UA BF 50
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.