Datasheet

PIC18F45J10 FAMILY
DS39682E-page 10 © 2009 Microchip Technology Inc.
FIGURE 1-1: PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA5/AN4/S
S1/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
(1 Kbyte)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
PCLATU
PCU
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
RB4/KBI0/AN11
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator
MSSP
10-Bit
ADC
Timer2Timer1Timer0
CCP2CCP1
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
(2)
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
Block
INTRC
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
BOR
(2)
OSC1
OSC2
V
DD,VSS
MCLR
T1OSI
T1OSO
VDDCORE