Datasheet

PIC18F45J10 FAMILY
DS39682E-page 112 © 2009 Microchip Technology Inc.
TABLE 10-11: PORTE I/O SUMMARY
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/RD
/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input.
1 I ST PORTE<0> data input; disabled when analog input enabled.
RD
1 I TTL PSP read enable input (PSP enabled).
AN5 1 I ANA A/D Input Channel 5; default input configuration on POR.
RE1/WR
/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input.
1 I ST PORTE<1> data input; disabled when analog input enabled.
WR
1 I TTL PSP write enable input (PSP enabled).
AN6 1 I ANA A/D Input Channel 6; default input configuration on POR.
RE2/CS
/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input.
1 I ST PORTE<2> data input; disabled when analog input enabled.
CS
1 I TTL PSP write enable input (PSP enabled).
AN7 1 I ANA A/D Input Channel 7; default input configuration on POR.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE
(1)
— — — — — RE2 RE1 RE0 50
LATE
(1)
— — — — — PORTE Data Latch Register
(Read and Write to Data Latch)
50
TRISE
(1)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers are not available in 28-pin devices.