Datasheet

PIC18F45J10 FAMILY
DS39682E-page 108 © 2009 Microchip Technology Inc.
TABLE 10-9: PORTD I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PSP0/SCK2/
SCL2
RD0 0 O DIG LATD<0> data output.
1 I ST PORTD<0> data input.
PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data.
x I TTL PSP write data input.
SCK2 0 O DIG SPI clock output (MSSP2 module); takes priority over port data.
1 I ST SPI clock input (MSSP2 module).
SCL2 0 ODIGI
2
C™ clock output (MSSP2 module); takes priority over port data.
1 II
2
C/SMB I
2
C clock input (MSSP2 module); input type depends on module setting.
RD1/PSP1/SDI2/
SDA2
RD1 0 O DIG LATD<1> data output.
1 I ST PORTD<1> data input.
PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data.
x I TTL PSP write data input.
SDI2 1 I ST SPI data input (MSSP2 module).
SDA2 1 ODIGI
2
C data output (MSSP2 module); takes priority over port data.
1 II
2
C/SMB I
2
C data input (MSSP2 module); input type depends on module setting.
RD2/PSP2/SDO2 RD2 0 O DIG LATD<2> data output.
1 I ST PORTD<2> data input.
PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data.
x I TTL PSP write data input.
SDO2 0 O DIG SPI data output (MSSP2 module); takes priority over port data.
RD3/PSP3/SS2
RD3 0 O DIG LATD<3> data output.
1 I ST PORTD<3> data input.
PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data.
x I TTL PSP write data input.
SS2
1 I TTL Slave select input for MSSP2 (MSSP2 module).
RD4/PSP4 RD4 0 O DIG LATD<4> data output.
1 I ST PORTD<4> data input.
PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data.
x I TTL PSP write data input.
RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output.
1 I ST PORTD<5> data input.
PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data.
x I TTL PSP write data input.
P1B 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output.
1 I ST PORTD<6> data input.
PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data.
x I TTL PSP write data input.
P1C 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output.
1 I ST PORTD<7> data input.
PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data.
x I TTL PSP write data input.
P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer;
I
2
C™/SMB = I
2
C/SMBus input buffer;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).