Datasheet

PIC18F2585/2680/4585/4680
DS80202G-page 8 © 2007 Microchip Technology Inc.
24. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE (BAUDCON<1>) bit, the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high transi-
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two work arounds available:
1. After the wake-up event has occurred, clear
the WUE bit in software before reading the
receive buffer RCREG.
2. Poll the WUE bit and read RCREG after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
25. Module: Timer1
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
(T1CON<7>).
2. Use the internal clock synchronization option
by clearing the T1SYNC
bit (T1CON<2>).
Date Codes that pertain to this issue:
All engineering and production devices.
26. Module: MSSP
In an I
2
C system with multiple slave nodes, an
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and the SSPOV bits. In
both situations, the SSPIF bit is not set and an
interrupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I
2
C slave must clear the SSPOV bit after each
I
2
C event to maintain normal operation.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: MSSP
It has been observed that following a Power-on
Reset, I
2
C mode may not initialize properly by just
configuring the SCL and SDA pins as either inputs
or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application’s power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
2
C operation:
1. Configure the SCL and SDA pins as outputs by
clearing their corresponding TRIS bits.
2. Force SCL and SDA low by clearing the
corresponding LAT bits.
3. While keeping the LAT bits clear, configure
SCL and SDA as inputs by setting their TRIS
bits.
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
2
C
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: RCIF can only be cleared by reading
RCREG.