Datasheet

PIC18F2585/2680/4585/4680
DS80202G-page 4 © 2007 Microchip Technology Inc.
14. Module: MSSP
RCEN becomes set when the system is idle. In
normal operation, the setting of RCEN should be
ignored by the module while the system is not idle.
Work around
Wait for the system to become idle. This requires
a check for the following bits to be reset:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: MSSP
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
16. Module: DC Characteristics (BOR)
The values for parameter D005 (VBOR) in
Section 27.1 “DC Characteristics: Supply
Voltage” of the Device Data Sheet, when the trip
point for BORV1:BORV0 = 11, are not applicable
as the device may reset below the minimum
operating voltage for the device.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
17. Module: BOR/HLVD
Due to production tolerances, selecting the lowest
setting for Brown-out Reset (BORV1:BORV0 = 11)
or Low-Voltage Reset (LVV = 0000) is not recom-
mended, since it may result in an actual Brown-out
Reset or Low-Voltage Detect below the minimum
allowable V
DD of 2.0V.
Work around
Use the next highest BOR or HLVD voltage thresh-
old to ensure a low V
DD is detected before it drops
below 2.0V.
Date Codes that pertain to this issue:
All engineering and production devices.
18. Module: ECCP
When operating either Timer1 or Timer3 as a
counter, with a prescale value other than 1:1, and
operating the ECCP in Compare mode, with the
Special Event Trigger (CCP1CON bits
CCP1M3:CCP1M0 = 1011), the Special Event
Trigger Reset of the timer occurs as soon as there
is a match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the Special
Event Trigger Reset of the timer occurs on the next
rollover of the prescale counter, after the match
between TMRxH:TMRxL and CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period on the
PIC18F4680 family as the PIC18F458 family for a
given clock source, add 1 to the value in
CCPR1H:CCPR1L.
In other words, if CCPR1H:CCPR1L = x for the
PIC18F458, to achieve the same Reset period on
the PIC18F4680 family, CCPR1H:CCPR1L = x + 1,
where the prescale is 1, 2, 4 or 8 depending on the
T1CKPS1:T1CKPS0 bit values.
Date Codes that pertain to this issue:
All engineering and production devices