Datasheet
© 2007 Microchip Technology Inc. DS80202G-page 3
PIC18F2585/2680/4585/4680
11. Module: MSSP
When the MSSP is configured for SPI Master
mode, the SDO pin cannot be disabled by setting
the TRISC<5> bit. The SDO pin always outputs
the content of SSPBUF regardless of the state of
the TRIS bit.
In Slave mode with slave select enabled,
SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the
SDO pin can be disabled by placing a logic high
level on the SS
pin (RA5).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices
12. Module: MSSP
After an I
2
C™ transfer is initiated, the SSPBUF
register may be written for up to 10 T
CY before
additional writes are blocked. The data transfer
may be corrupted if SSPBUF is written to during
this time.
The WCOL bit is set anytime an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
13. Module: MSSP
In its current implementation, the I
2
C Master mode
operates as follows:
1. The Baud Rate Generator for I
2
C in Master
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 1 in place of those shown in
Table 17-3 of the Device Data Sheet. The
differences are shown in bold text.
2. Use the following formula in place of the one
shown in Register 17-4 (SSPCON1) of the
Device Data Sheet for bit description,
SSPM3:SSPM0 = 1000.
SSPADD = INT((F
CY/FSCL) – (FCY/1.111 MHz)) – 1
TABLE 1: I
2
C™ CLOCK RATE w/BRG
FOSC FCY FCY * 2 BRG Value
F
SCL
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 0Eh 400 kHz
(1)
40 MHz 10 MHz 20 MHz 15h 312.5 kHz
40 MHz 10 MHz 20 MHz 59h 100 kHz
16 MHz 4 MHz 8 MHz 05h 400 kHz
(1)
16 MHz 4 MHz 8 MHz 08h 308 kHz
16 MHz 4 MHz 8 MHz 23h 100 kHz
4 MHz 1 MHz 2 MHz 01h 333 kHz
(1)
4 MHz 1 MHz 2 MHz 08h 100 kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz
(1)
Note 1: The I
2
C™ interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.