Information

© 2007 Microchip Technology Inc. DS80283E-page 9
PIC18F2585/2680/4585/4680
29. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 27.1 “DC Characteristics: Supply
Voltage” of the Device Data Sheet. The RAM
content may be altered during a Reset event if the
following conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
30. Module: ECAN™ Technology
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the Transmit Buffer ID register, TXBnSIDH. The
following conditions must exist for the corruption to
occur:
1. A transmit message must be pending.
2. The ECAN module must detect a Start-Of-
Frame (SOF) in the third bit of interframe
space.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
31. Module: ECAN™ Technology
Following an error on the bus, the ECAN module is
unable to switch from Listen Only mode directly to
Configuration mode.
Work around
Use the REQOP (CANCON<7:5>) bits to select
Normal mode as an intermediate step when
switching from Listen Only mode to Configuration
mode.
Date Codes that pertain to this issue:
All engineering and production devices.
32. Module: ECAN™ Technology
Under specific conditions, the TXBxSIDH register
of the pending message for transmission may be
corrupted. The following conditions must exist for
this event to occur:
1. A transmit message must be pending.
2. All of the receive buffers must be full and a
received message is in the Message Assembly
Buffer (MAB).
3. A receiver buffer must be made available
(RXBxCON<RXFUL> set to '0') when a Start-
of-Frame (SOF) is recognized on the CAN bus,
or on the instruction cycle prior to the SOF for
the TXBxSIDH corruption event to occur. The
timing of this event is crucial.
Work around
Ensure that a receive buffer overflow condition
does not occur and/or ensure that a transmit
request is not pending if a receive buffer overflow
condition does exist.
The pseudo-code segment in Example 6 is an
example of how to disable a pending transmission.
This code is for illustration purposes only.
Date Codes that pertain to this issue:
All engineering and production devices.
EXAMPLE 6:
If (RXBnOVFL == 1) // Has an overflow occurred?
{ If (TXREQ == 1)// Is a transmission pending?
{ TXREQ = 0; // Clear transmit request
If (TXABT == 1)// Store transmission aborted status value
MyFlag = 1;
}
}
Temp_RXREG = RXBx; // Read receive buffer
If (MyFlag) // Was previous transmission aborted?
{ TXREQ = 1; // Set transmit request
MyFlag = 0; // Reset stored transmission aborted status
}