Information

PIC18F2585/2680/4585/4680
DS80283E-page 8 © 2007 Microchip Technology Inc.
25. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXIF. This is because any write to the
TXSTA register results in a reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when a transmission is not in progress
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
26. Module: EUSART
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE (BAUDCON<1>) bit, the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high transi-
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two work arounds available:
1. After the wake-up event has occurred, clear
the WUE bit in software before reading the
receive buffer RCREG.
2. Poll the WUE bit and read RCREG after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
28. Module: EUSART
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted, only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer TXREG are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to,
• the baud rate counter overflows (at the end of
the bit period), and
• a Stop bit is being transmitted (shifted out of
TSR).
Work around
If possible, do not use the module’s double buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREG
immediately after TXIF is set or wait 1-bit time after
TXIF is set. Both solutions prevent writing TXREG
while a Stop bit is transmitted. Note that TXIF is set
at the beginning of the Stop bit transmission.
If transmission is intermittent, then do the
following:
• Wait for the TRMT bit to be set before
loading TXREG.
• Alternatively, use a free timer resource to
time the baud period. Set up the timer to
overflow at the end of the Stop bit, then start
the timer when you load the TXREG. Do not
load the TXREG when timer is about to
overflow.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: RCIF can only be cleared by reading
RCREG.