Information

© 2007 Microchip Technology Inc. DS80272B-page 5
PIC18F2585/2680/4585/4680
4. Module: Master Synchronous Serial Port
(MSSP) – Serial Peripheral
Interface (SPI)
The following note has been added to the end of
Section 17.3.3 “Enabling SPI I/O”.
5. Module: Enhanced
Capture/Compare/PWM (ECCP1)
Module
The following note has been added to the end of
Section 16.4.6 “Programmable Dead-Band
Delay”.
Note: When the module is enabled and in
Master mode (CKE, SSPSTAT<6> = 1), a
small glitch of approximately half a TCY
may be seen on the SCK pin. To resolve
this, keep the SCK pin as an input while
setting SPEN. Then, configure the SCK
pin as an output (TRISC<3> = 0).
Note: If the dead-band delay value is increased
after the dead-band time has elapsed, that
new value takes effect immediately. This
happens even if the PWM pulse is high
and can appear to be a glitch.
Dead-band values must be changed
during the dead-band time or before the
ECCP1 module is active.