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PIC18FXX8

The PIC18FXX8 Rev. B4 parts you have received

conform functionally to the Device Data Sheet

(DS41159D), except for the anomalies described

below.

All of the issues listed here will be addressed in future

revisions of the PIC18FXX8 silicon.

The following silicon errata apply only to

PIC18FXX8 devices with these Device/Revision

IDs:

1. Module: ECCP

When the ECCP module is operating in Half-

Bridge mode, use of a dead-band delay other than

zero will have the effect of introducing an

unintended pulse on the P1A and P1B signals.

Work around

Disable the dead-band delay by ensuring that the

ECCP1DEL register is set to 00h.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: I/O (Parallel Slave Port)

The Input Buffer Full Status bit, IBF, of the TRISE

even when the PORTE input buffer has not been

read. This will occur only when the following two

conditions occur simultaneously:

• The four Least Significant bits of the BSR

and

• Any instruction that contains 83h in its 8 Least

Significant bits (i.e., register file addresses,

literal data, address offsets, etc.) is executed.

Work around

All work arounds will involve setting the contents of

BSR<3:0> to some value other than 0Fh. In

addition to those proposed below, other solutions

may exist.

1. When developing or modifying code, keep

these guidelines in mind:

• Assign 12-bit addresses to all variables.

This allows the assembler to know when

Access Banking can be used.

• Do not set the BSR to point to Bank 15

(BSR = 0Fh).

• Allow the assembler to manipulate the

Access bit present in most instructions.

Accessing the SFRs in Bank 15 will be done

through the Access Bank. Continue to use

the BSR to select Banks 1 through 5 and

the upper half of Bank 0.

2. If accessing a part of Bank 15 is required, and

the use of Access Banking is not possible,

consider using Indirect Addressing mode.

3. If pointing the BSR to Bank 15 is unavoidable,

review the absolute file listing. Verify that no

instructions contain 83h in the 8 Least

Significant bits while the BSR points to Bank 15

(BSR = 0Fh).

Part Number Device ID Revision ID

PIC18F248 00 1000 000 00100

PIC18F258 00 1000 010 00100

PIC18F448 00 1000 001 00100

PIC18F458 00 1000 011 00100

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18FXX8 Rev. B4 Silicon Errata Sheet

Summary of content (8 pages)

PAGE 1
PIC18FXX8 PIC18FXX8 Rev. B4 Silicon Errata Sheet The PIC18FXX8 Rev. B4 parts you have received conform functionally to the Device Data Sheet (DS41159D), except for the anomalies described below. All of the issues listed here will be addressed in future revisions of the PIC18FXX8 silicon.
PAGE 2
PIC18FXX8 3. Module: Core (Program Memory Space) Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the device’s rated temperature range (-40°C). This applies specifically to addresses above 1FFFFFh, including the user ID locations (200000h-200007h), the configuration bytes (300000h-30000Dh) and the device ID locations (3FFFFEh and 3FFFFFh). User program memory is unaffected.
PAGE 3
PIC18FXX8 7. Module: A/D (External Voltage Reference) and Comparator Voltage Reference When the external voltage reference, VREF-, is selected for use with either the A/D or comparator voltage reference, AVSS is connected to VREF- in the comparator module. If VREF- is a voltage other than AVSS (which must be tied externally to VSS), excessive current will flow into the VREF- pin.
PAGE 4
PIC18FXX8 10. Module: MSSP (SPI, Slave Mode) In its current implementation, the SS (Slave Select) control signal generated by an external master processor may not be successfully recognized by the PIC® microcontroller operating in Slave Select mode (SSPM3:SSPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall times) are more likely to be missed than than slower transitions.
PAGE 5
PIC18FXX8 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS41159D), the following clarifications and corrections should be noted. None. © 2006 Microchip Technology Inc.
PAGE 6
PIC18FXX8 REVISION HISTORY Rev A Document (7/2002) First revision of this document, silicon issues 1 (ECCP), 2 (I/O – Parallel Slave Port) and 3 (Core – Program Memory Space). Rev B Document (11/2002) Added silicon issues 4, 5, 6 and 7 (Core – Program Memory Space and Data EEPROM). Rev C Document (03/2003) Added silicon issue 7 (A/D (External Voltage Reference) and Comparator Voltage Reference) and data sheet clarification issue 1 (A/D – VREF+ and VREFReferences).
PAGE 7
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 8
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