Datasheet

PIC18FXX8
DS41159E-page 92 © 2006 Microchip Technology Inc.
8.6 INT Interrupts
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/CANTX/INT2 pins are edge triggered: either rising
if the corresponding INTEDGx bit is set in the
INTCON2 register, or falling if the INTEDGx bit is clear.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit INTxIF is set. This interrupt can
be disabled by clearing the corresponding enable bit
INTxIE. Flag bit INTxIF must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1 and INT2)
can wake-up the processor from Sleep if bit INTxIE was
set prior to going into Sleep. If the Global Interrupt
Enable bit, GIE, is set, the processor will branch to the
interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0; it is always a high
priority interrupt source.
8.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 11.0 “Timer0 Module” for further details.
8.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-on-
change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
8.9 Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 4.3 “Fast
Register Stack”), the user may need to save the
WREG, Status and BSR registers in software. Depend-
ing on the user’s application, other registers may also
need to be saved. Example 8-1 saves and restores the
WREG, Status and BSR registers during an Interrupt
Service Routine.
EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in Low Access bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS