Datasheet

© 2006 Microchip Technology Inc. DS41159E-page 89
PIC18FXX8
REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—CMIP
(1)
— EEIP BCLIP LVDIP TMR3IP ECCP1IP
(1)
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIP: Comparator Interrupt Priority bit
(1)
1 =High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIP: EEPROM Write Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 ECCP1IP: ECCP1 Interrupt Priority bit
(1)
1 =High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown