Datasheet

© 2006 Microchip Technology Inc. DS41159E-page 49
PIC18FXX8
TABLE 4-2: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
Page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 30, 38
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 30, 38
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 30, 38
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 30, 39
PCLATU
— —bit 21
(2)
Holding Register for PC<20:16> ---0 0000 30, 40
PCLATH Holding Register for PC<15:8> 0000 0000 30, 40
PCL PC Low Byte (PC<7:0>) 0000 0000 30, 40
TBLPTRU
— —bit 21
(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 30, 68
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 30, 68
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 30, 68
TABLAT Program Memory Table Latch 0000 0000 30, 68
PRODH Product Register High Byte xxxx xxxx 30, 75
PRODL Product Register Low Byte xxxx xxxx 30, 75
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 30, 79
INTCON2 RBPU
INTEDG0 INTEDG1 — —TMR0IP—RBIP111- -1-1 30, 80
INTCON3 INT2IP INT1IP
—INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 30, 81
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 30, 55
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 30, 55
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 30, 55
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 30, 55
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 30, 55
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 30, 55
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 30, 55
WREG Working Register xxxx xxxx 30, 55
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 30, 55
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 30, 55
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 30, 55
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 30, 55
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 30, 55
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 31, 55
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 31, 55
BSR
— — — — Bank Select Register ---- 0000 31, 54
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 31, 55
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 31, 55
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 31, 55
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 31, 55
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 31, 55
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 31, 55
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 31, 55
STATUS
— — —NOVZDCC---x xxxx 31, 57
TMR0H Timer0 Register High Byte 0000 0000 31, 111
TMR0L Timer0 Register Low Byte xxxx xxxx 31, 111
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 31, 109
OSCCON
— — — — — — —SCS---- ---0 31, 20
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 31, 261
WDTCON
— — — — — — —SWDTEN---- ---0 31, 272
RCON IPEN
— —RITO PD POR BOR 0--1 110q 31, 58, 91
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.