Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 40 MHz I/O number 22

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Table Of Contents

High-Performance RISC CPU:
Peripheral Features:
Advanced Analog Features:
CAN bus Module Features:
Special Microcontroller Features:
Flash Technology:
Pin Diagrams
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- TABLE 1-1: PIC18FXX8 Device Features
- FIGURE 1-1: PIC18F248/258 Block Diagram
- FIGURE 1-2: PIC18F448/458 Block Diagram
- TABLE 1-2: PIC18FXX8 Pinout I/O Descriptions
2.0 Oscillator Configurations
- 2.1 Oscillator Types
- 2.2 Crystal Oscillator/Ceramic Resonators
- 2.3 RC Oscillator
  - FIGURE 2-2: RC Oscillator Mode
- 2.4 External Clock Input
  - FIGURE 2-3: External Clock Input Operation (EC Osc Configuration)
  - FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
- 2.5 HS4 (PLL)
  - FIGURE 2-5: PLL Block Diagram
- 2.6 Oscillator Switching Feature
  - 2.6.1 System Clock Switch Bit
    - FIGURE 2-6: Device Clock Sources
    - Register 2-1: OSCCON: Oscillator Control Register
  - 2.6.2 Oscillator Transitions
- 2.7 Effects of Sleep Mode on the OnChip Oscillator
- 2.8 Power-up Delays
  - TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
3.0 Reset
- FIGURE 3-1: Simplified Block Diagram of On-Chip Reset Circuit
- 3.1 Power-on Reset (POR)
- 3.2 MCLR
  - FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 3.3 Power-up Timer (PWRT)
- 3.4 Oscillator Start-up Timer (OST)
- 3.5 PLL Lock Time-out
- 3.6 Brown-out Reset (BOR)
- 3.7 Time-out Sequence
4.0 Memory Organization
- 4.1 Program Memory Organization
  - FIGURE 4-1: Program Memory Map and Stack for PIC18F248/448
  - 4.1.1 Internal Program Memory Operation
    - FIGURE 4-2: Program Memory Map and Stack for PIC18F258/458
- 4.2 Return Address Stack
- 4.3 Fast Register Stack
  - EXAMPLE 4-1: Fast Register Stack Code Example
- 4.4 PCL, PCLATH and PCLATU
- 4.5 Clocking Scheme/Instruction Cycle
  - FIGURE 4-4: Clock/Instruction Cycle
- 4.6 Instruction Flow/Pipelining
- 4.7 Instructions in Program Memory
- 4.8 Look-up Tables
  - 4.8.1 Computed GOTO
  - 4.8.2 Table Reads/Table Writes
    - EXAMPLE 4-4: Two-Word Instructions
- 4.9 Data Memory Organization
  - 4.9.1 General Purpose Register File
  - 4.9.2 Special Function Registers
- 4.10 Access Bank
- 4.11 Bank Select Register (BSR)
  - FIGURE 4-7: Direct Addressing
- 4.12 Indirect Addressing, INDF and FSR Registers
  - EXAMPLE 4-5: How to Clear RAM (Bank 1) Using Indirect Addressing
  - 4.12.1 Indirect Addressing Operation
    - FIGURE 4-8: Indirect Addressing
- 4.13 Status Register
  - Register 4-2: Status Register
- 4.14 RCON Register
  - Register 4-3: RCON: Reset Control Register
5.0 Data EEPROM Memory
- 5.1 EEADR Register
- 5.2 EECON1 and EECON2 Registers
  - Register 5-1: EECON1: EEPROM Control Register 1
- 5.3 Reading the Data EEPROM Memory
  - EXAMPLE 5-1: Data EEPROM Read
- 5.4 Writing to the Data EEPROM Memory
  - EXAMPLE 5-2: Data EEPROM Write
- 5.5 Write Verify
- 5.6 Protection Against Spurious Write
- 5.7 Operation During Code-Protect
- 5.8 Using the Data EEPROM
  - EXAMPLE 5-3: Data EEPROM Refresh Routine
  - TABLE 5-1: Registers Associated with Data EEPROM Memory
6.0 Flash Program Memory
- 6.1 Table Reads and Table Writes
  - FIGURE 6-1: Table Read Operation
  - FIGURE 6-2: Table Write Operation
- 6.2 Control Registers
- 6.3 Reading the Flash Program Memory
  - FIGURE 6-4: Reads From Flash Program Memory
  - EXAMPLE 6-1: Reading a Flash Program Memory Word
- 6.4 Erasing Flash Program Memory
  - 6.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 6-2: Erasing a Flash Program Memory Row
- 6.5 Writing to Flash Program Memory
- 6.6 Flash Program Operation During Code Protection
  - TABLE 6-2: Registers Associated with Program Flash Memory
7.0 8 x 8 Hardware Multiplier
- 7.1 Introduction
- 7.2 Operation
8.0 Interrupts
- FIGURE 8-1: Interrupt Logic
- 8.1 INTCON Registers
- 8.2 PIR Registers
- 8.3 PIE Registers
- 8.4 IPR Registers
- 8.5 RCON Register
  - Register 8-13: RCON: Reset Control Register
- 8.6 INT Interrupts
- 8.7 TMR0 Interrupt
- 8.8 PORTB Interrupt-on-Change
- 8.9 Context Saving During Interrupts
  - EXAMPLE 8-1: Saving Status, WREG and BSR Registers in RAM
9.0 I/O Ports
- 9.1 PORTA, TRISA and LATA Registers
- 9.2 PORTB, TRISB and LATB Registers
- 9.3 PORTC, TRISC and LATC Registers
- 9.4 PORTD, TRISD and LATD Registers
- 9.5 PORTE, TRISE and LATE Registers
10.0 Parallel Slave Port
- FIGURE 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)
- FIGURE 10-2: Parallel Slave Port Write Waveforms
- FIGURE 10-3: Parallel Slave Port Read Waveforms
- TABLE 10-1: Registers Associated with Parallel Slave Port
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode
- FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode
- 11.1 Timer0 Operation
- 11.2 Prescaler
  - 11.2.1 Switching Prescaler Assignment
- 11.3 Timer0 Interrupt
- 11.4 16-Bit Mode Timer Reads and Writes
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram
  - FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode
- 12.2 Timer1 Oscillator
  - TABLE 12-1: Capacitor Selection for the Alternate Oscillator
- 12.3 Timer1 Interrupt
- 12.4 Resetting Timer1 Using a CCP Trigger Output
- 12.5 Timer1 16-Bit Read/Write Mode
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Output of TMR2
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON:Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram
  - FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit Read/Write Mode
- 14.2 Timer1 Oscillator
- 14.3 Timer3 Interrupt
- 14.4 Resetting Timer3 Using a CCP Trigger Output
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Capture/Compare/PWM (CCP) Modules
- Register 15-1: CCP1CON: CCP1 Control Register
- 15.1 CCP1 Module
  - TABLE 15-1: CCP1 Mode – Timer Resource
- 15.2 Capture Mode
- 15.3 Compare Mode
- 15.4 PWM Mode
16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 16-1: ECCP1Con: ECCP1 Control Register
- 16.1 ECCP1 Module
- 16.2 Capture Mode
  - 16.2.1 CAN Message TIME-STAMP
- 16.3 Compare Mode
  - 16.3.1 Special Event Trigger
    - TABLE 16-4: Registers Associated with Enhanced Capture, Compare, Timer1 and Timer3
- 16.4 Standard PWM Mode
- 16.5 Enhanced PWM Mode
- 16.6 Enhanced CCP Auto-Shutdown
  - Register 16-3: ECCPAS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register
17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- 17.4 I2C Mode
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
- Register 18-1: TXSTA: Transmit Status and Control Register
- Register 18-2: RCSTA: Receive Status and Control Register
- 18.1 USART Baud Rate Generator (BRG)
  - 18.1.1 Sampling
- 18.2 USART Asynchronous Mode
- 18.3 USART Synchronous Master Mode
  - 18.3.1 USART Synchronous Master Transmission
  - 18.3.2 USART Synchronous Master Reception
    - TABLE 18-9: Registers Associated with Synchronous Master Reception
    - FIGURE 18-8: Synchronous Reception (Master Mode, SREN)
- 18.4 USART Synchronous Slave Mode
  - 18.4.1 USART Synchronous Slave Transmit
  - 18.4.2 USART Synchronous Slave Reception
    - TABLE 18-10: Registers Associated with Synchronous Slave Transmission
    - TABLE 18-11: Registers Associated with Synchronous Slave Reception
19.0 CAN Module
- 19.1 Overview
  - 19.1.1 Overview of the Module
  - 19.1.2 Transmit/Receive Buffers
    - FIGURE 19-1: CAN Buffers and Protocol Engine Block Diagram
- 19.2 CAN Module Registers
- 19.3 CAN Modes of Operation
- 19.4 CAN Message Transmission
- 19.5 Message Reception
- 19.6 Message Acceptance Filters and Masks
  - TABLE 19-2: Filter/Mask Truth Table
  - FIGURE 19-6: Message Acceptance Mask and Filter Operation
- 19.7 Baud Rate Setting
- 19.8 Synchronization
- 19.9 Programming Time Segments
- 19.10 Oscillator Tolerance
- 19.11 Bit Timing Configuration Registers
- 19.12 Error Detection
- 19.13 CAN Interrupts
20.0 Compatible 10-Bit Analog- to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- FIGURE 20-1: A/D Block Diagram
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting the A/D Conversion Clock
- 20.3 Configuring Analog Port Pins
  - TABLE 20-1: Tad vs. Device Operating Frequencies
  - TABLE 20-2: Tad vs. Device Operating Frequencies (for Extended, LF Devices)
- 20.4 A/D Conversions
  - 20.4.1 A/D Result Registers
    - FIGURE 20-3: A/D Result Justification
- 20.5 Use of the ECCP Trigger
  - FIGURE 20-4: A/D Conversion Tad Cycles
  - TABLE 20-3: Summary of A/D Registers
21.0 Comparator Module
- Register 21-1: CMCON: Comparator Control Register
- 21.1 Comparator Configuration
  - FIGURE 21-1: Comparator I/O Operating Modes
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
  - FIGURE 21-3: Comparator Output Block Diagram
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
  - FIGURE 21-4: Analog Input Model
  - TABLE 21-1: Registers Associated with Comparator Module
22.0 Comparator Voltage Reference Module
- 22.1 Configuring the Comparator Voltage Reference
- 22.2 Voltage Reference Accuracy/Error
- 22.3 Operation During Sleep
- 22.4 Effects of a Reset
- 22.5 Connection Considerations
  - FIGURE 22-2: Voltage Reference Output Buffer Example
  - TABLE 22-1: Registers Associated with Comparator Voltage Reference
23.0 Low-Voltage Detect
- FIGURE 23-1: Typical Low-Voltage Detect Application
- FIGURE 23-2: Low-Voltage Detect (LVD) Block Diagram
- FIGURE 23-3: Low-Voltage Detect (LVD) with External Input Block Diagram
- 23.1 Control Register
  - Register 23-1: LVDCON: Low-Voltage Detect Control Register
- 23.2 Operation
- 23.3 Operation During Sleep
- 23.4 Effects of a Reset
24.0 Special Features of the CPU
- 24.1 Configuration Bits
- 24.2 Watchdog Timer (WDT)
  - 24.2.1 Control Register
    - Register 24-13: WDTCON: Watchdog Timer Control Register
  - 24.2.2 WDT Postscaler
    - FIGURE 24-1: Watchdog Timer Block Diagram
    - TABLE 24-2: Summary of Watchdog Timer Registers
- 24.3 Power-Down Mode (Sleep)
  - 24.3.1 Wake-up From Sleep
  - 24.3.2 Wake-up Using Interrupts
    - FIGURE 24-2: Wake-up From Sleep Through Interrupt(1,2)
- 24.4 Program Verification and Code Protection
- 24.5 ID Locations
- 24.6 In-Circuit Serial Programming
- 24.7 In-Circuit Debugger
- 24.8 Low-Voltage ICSP Programming
25.0 Instruction Set Summary
- 25.1 ReadModify-Write Operations
- 25.2 Instruction Set
26.0 Development Support
- 26.1 MPLAB Integrated Development Environment Software
- 26.2 MPASM Assembler
- 26.3 MPLAB C17 and MPLAB C18 C Compilers
- 26.4 MPLINK Object Linker/ MPLIB Object Librarian
- 26.5 MPLAB C30 C Compiler
- 26.6 MPLAB ASM30 Assembler, Linker and Librarian
- 26.7 MPLAB SIM Software Simulator
- 26.8 MPLAB SIM30 Software Simulator
- 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
- 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
- 26.11 MPLAB ICD 2 In-Circuit Debugger
- 26.12 PRO MATE II Universal Device Programmer
- 26.13 MPLAB PM3 Device Programmer
- 26.14 PICSTART Plus Development Programmer
- 26.15 PICDEM 1 PICmicro Demonstration Board
- 26.16 PICDEM.net Internet/Ethernet Demonstration Board
- 26.17 PICDEM 2 Plus Demonstration Board
- 26.18 PICDEM 3 PIC16C92X Demonstration Board
- 26.19 PICDEM 4 8/14/18-Pin Demonstration Board
- 26.20 PICDEM 17 Demonstration Board
- 26.21 PICDEM 18R PIC18C601/801 Demonstration Board
- 26.22 PICDEM LIN PIC16C43X Demonstration Board
- 26.23 PICkitTM 1 Flash Starter Kit
- 26.24 PICDEM USB PIC16C7X5 Demonstration Board
- 26.25 Evaluation and Programming Tools
27.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 27.1 DC Characteristics
- 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
- 27.3 AC (Timing) Characteristics
28.0 DC and AC Characteristics Graphs and Tables
- FIGURE 28-1: Typical Idd vs. Fosc Over Vdd (Hs Mode)
- FIGURE 28-2: Maximum Idd vs. Fosc Over Vdd (Hs Mode)
- FIGURE 28-3: Typical Idd vs. Fosc Over Vdd (HS/PLL Mode)
- FIGURE 28-4: Maximum Idd vs. Fosc Over Vdd (HS/PLL Mode)
- FIGURE 28-5: Typical Idd vs. Fosc Over Vdd (XT Mode)
- FIGURE 28-6: Maximum Idd vs. Fosc Over Vdd (XT Mode)
- FIGURE 28-7: Typical Idd vs. Fosc Over Vdd (LP Mode)
- FIGURE 28-8: Maximum Idd vs. Fosc Over Vdd (LP Mode)
- FIGURE 28-9: Typical Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 28-10: Maximum Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 28-11: Typical and Maximum Idd vs. Vdd (Timer1 as Main Oscillator 32.768kHz, C1 and C2 = ...
- FIGURE 28-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25°C)
- FIGURE 28-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25°C)
- FIGURE 28-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25°C)
- FIGURE 28-15: Ipd vs. Vdd, -40°C to +125°C (Sleep Mode, All Peripherals Disabled)
- FIGURE 28-16: DIbor vs. Vdd Over Temperature (BOR Enabled, Vbor = 2.00-2.16V)
- FIGURE 28-17: Typical and Maximum DItmr1 vs. Vdd Over Temperature (-10°C to +70°C, Timer1 with Os...
- FIGURE 28-18: Typical and Maximum DIwdt vs. Vdd Over Temperature (WDT Enabled)
- FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)
- FIGURE 28-20: DIlvd vs. Vdd Over Temperature (LVD Enabled, Vlvd = 4.5 - 4.78V)
- FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C)
- FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C)
- FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C)
- FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C)
- FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)
- FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40°C to +125°C)
- FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C™ Input, -40°C to +125°C)
- FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40°C to +125°C)
- FIGURE 28-29: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40°C to +125°C)
29.0 Packaging Information
- 29.1 Package Marking Information
- 29.1 Package Marking Information (Continued)
- 29.2 Package Details
- 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
- 28-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC)
- 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
- 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
- 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Appendix A: Data Sheet Revision History
- Revision A (June 2001)
- Revision B (May 2002)
- Revision C (January 2003)
- Revision D (September 2004)
- Revision E (October 2006)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Device Migrations
Appendix D: Migrating From Other PICmicro® Devices
INDEX
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PIC18FXX8

FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)

FIGURE 28-6: MAXIMUM I

DD vs. FOSC OVER VDD (XT MODE)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OSC

(MHz)

(mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3

σ (-40°C to +125°C)

Minimum: mean – 3