Datasheet

© 2006 Microchip Technology Inc. DS41159E-page 345
PIC18FXX8
FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 27-9: BROWN-OUT RESET AND LOW-VOLTAGE DETECT TIMING
TABLE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
BROWN-OUT RESET AND LOW-VOLTAGE DETECT REQUIREMENTS
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(no prescaler)
71833ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 28 72 132 ms
34 T
IOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—2—μs
35 T
BOR Brown-out Reset Pulse Width 200 — — μsFor VDD ≤ BVDD (see D005)
36 T
IRVST Time for Internal Reference
Voltage to become stable
—2050 μs
37 T
LVD Low-Voltage Detect Pulse Width 200 — — μsFor VDD ≤ VLVD (see D420)
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 27-5 for load conditions.
VDD
BVDD (for 35)
35, 37
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
VLVD (for 37)
Reference Voltage
Voltage Stable