Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Peripheral Features:
- Advanced Analog Features:
- CAN bus Module Features:
- Special Microcontroller Features:
- Flash Technology:
- Pin Diagrams
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Oscillator Configurations
- 3.0 Reset
- FIGURE 3-1: Simplified Block Diagram of On-Chip Reset Circuit
- 3.1 Power-on Reset (POR)
- 3.2 MCLR
- 3.3 Power-up Timer (PWRT)
- 3.4 Oscillator Start-up Timer (OST)
- 3.5 PLL Lock Time-out
- 3.6 Brown-out Reset (BOR)
- 3.7 Time-out Sequence
- TABLE 3-1: Time-out in Various Situations
- Register 3-1: RCON Register Bits and Positions
- TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
- FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)
- FIGURE 3-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
- FIGURE 3-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
- FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd)
- FIGURE 3-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)
- TABLE 3-3: Initialization Conditions for All Registers
- 4.0 Memory Organization
- 4.1 Program Memory Organization
- 4.2 Return Address Stack
- 4.3 Fast Register Stack
- 4.4 PCL, PCLATH and PCLATU
- 4.5 Clocking Scheme/Instruction Cycle
- 4.6 Instruction Flow/Pipelining
- 4.7 Instructions in Program Memory
- 4.8 Look-up Tables
- 4.9 Data Memory Organization
- 4.10 Access Bank
- 4.11 Bank Select Register (BSR)
- 4.12 Indirect Addressing, INDF and FSR Registers
- 4.13 Status Register
- 4.14 RCON Register
- 5.0 Data EEPROM Memory
- 6.0 Flash Program Memory
- 6.1 Table Reads and Table Writes
- 6.2 Control Registers
- 6.3 Reading the Flash Program Memory
- 6.4 Erasing Flash Program Memory
- 6.5 Writing to Flash Program Memory
- 6.6 Flash Program Operation During Code Protection
- 7.0 8 x 8 Hardware Multiplier
- 7.1 Introduction
- 7.2 Operation
- EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 7-2: 8 x 8 Signed Multiply Routine
- TABLE 7-1: Performance Comparison
- EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 7-4: 16 x 16 Signed Multiply Routine
- 8.0 Interrupts
- 9.0 I/O Ports
- 10.0 Parallel Slave Port
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Capture/Compare/PWM (CCP) Modules
- 16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 16-1: ECCP1Con: ECCP1 Control Register
- 16.1 ECCP1 Module
- 16.2 Capture Mode
- 16.3 Compare Mode
- 16.4 Standard PWM Mode
- 16.5 Enhanced PWM Mode
- 16.6 Enhanced CCP Auto-Shutdown
- 17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- 17.4 I2C Mode
- FIGURE 17-7: MSSP Block Diagram (I2C™ Mode)
- 17.4.1 Registers
- 17.4.2 Operation
- 17.4.3 Slave Mode
- 17.4.4 Clock Stretching
- 17.4.5 General Call Address Support
- 17.4.6 Master Mode
- 17.4.7 Baud Rate Generator
- 17.4.8 I2C Master Mode Start Condition Timing
- 17.4.9 I2C Master Mode Repeated Start Condition Timing
- 17.4.10 I2C Master Mode Transmission
- 17.4.11 I2C Master Mode Reception
- 17.4.12 Acknowledge Sequence Timing
- 17.4.13 Stop Condition Timing
- 17.4.14 Sleep Operation
- 17.4.15 Effect of a Reset
- 17.4.16 Multi-Master Mode
- 17.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 17-26: Bus Collision During Start Condition (SDA Only)
- FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)
- FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 17-30: Bus Collision During a Repeated Start Condition (Case 2)
- FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)
- FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)
- 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
- Register 18-1: TXSTA: Transmit Status and Control Register
- Register 18-2: RCSTA: Receive Status and Control Register
- 18.1 USART Baud Rate Generator (BRG)
- 18.2 USART Asynchronous Mode
- 18.3 USART Synchronous Master Mode
- 18.4 USART Synchronous Slave Mode
- 19.0 CAN Module
- 19.1 Overview
- 19.2 CAN Module Registers
- 19.2.1 CAN Control and Status Registers
- Register 19-1: CANCON: CAN Control Register
- Register 19-2: CANSTAT: CAN Status Register
- EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers
- EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...
- Register 19-3: COMSTAT: Communication Status Register
- 19.2.2 CAN Transmit Buffer Registers
- Register 19-4: TXBnCON: Transmit Buffer n Control Registers
- Register 19-5: TXBnSIDH: Transmit Buffer n Standard Identifier, High Byte Registers
- Register 19-6: TXBnSIDL: Transmit Buffer n Standard Identifier, Low Byte Registers
- Register 19-7: TXBnEIDH: Transmit Buffer n Extended Identifier, High Byte Registers
- Register 19-8: TXBnEIDL: Transmit Buffer n Extended Identifier, Low Byte Registers
- Register 19-9: TXBnDm: Transmit Buffer n Data Field Byte m Registers
- Register 19-10: TXBnDLC: Transmit Buffer N Data Length Code Registers
- Register 19-11: TXERRCNT: Transmit Error Count Register
- 19.2.3 CAN Receive Buffer Registers
- Register 19-12: RXB0CON: Receive Buffer 0 Control Register
- Register 19-13: RXB1CON: Receive Buffer 1 Control Register
- Register 19-14: RXBnSIDH: Receive Buffer N Standard Identifier, High Byte Registers
- Register 19-15: RXBnSIDL: Receive Buffer N Standard Identifier, Low Byte Registers
- Register 19-16: RXBnEIDH: Receive Buffer N Extended Identifier, High Byte Registers
- Register 19-17: RXBnEIDL: Receive Buffer N Extended Identifier, Low Byte Registers
- Register 19-18: RXBnDLC: Receive Buffer N Data Length Code Registers
- Register 19-19: RXBnDm: Receive Buffer N Data Field Byte M Registers
- Register 19-20: RXERRCNT: Receive Error Count Register
- Register 19-21: RXFnSIDH: Receive Acceptance Filter N Standard Identifier Filter, High Byte Regis...
- Register 19-22: RXFnSIDL: Receive Acceptance Filter N Standard Identifier Filter, Low Byte Registers
- Register 19-23: RXFnEIDH: Receive Acceptance Filter N Extended Identifier, High Byte Registers
- Register 19-24: RXFnEIDL: Receive Acceptance Filter N Extended Identifier, Low Byte Registers
- Register 19-25: RXMnSIDH: Receive Acceptance Mask N Standard Identifier Mask, High Byte Registers
- Register 19-26: RXMnSIDL: Receive Acceptance Mask N Standard Identifier Mask, Low Byte Registers
- Register 19-27: RXMnEIDH: Receive Acceptance Mask N Extended Identifier Mask, High Byte Registers
- Register 19-28: RXMnEIDL: Receive Acceptance Mask N Extended Identifier Mask, Low Byte Registers
- 19.2.4 CAN Baud Rate Registers
- 19.2.5 CAN Module I/O Control Register
- 19.2.6 CAN Interrupt Registers
- 19.2.1 CAN Control and Status Registers
- 19.3 CAN Modes of Operation
- 19.4 CAN Message Transmission
- 19.5 Message Reception
- 19.6 Message Acceptance Filters and Masks
- 19.7 Baud Rate Setting
- 19.8 Synchronization
- 19.9 Programming Time Segments
- 19.10 Oscillator Tolerance
- 19.11 Bit Timing Configuration Registers
- 19.12 Error Detection
- 19.13 CAN Interrupts
- 20.0 Compatible 10-Bit Analog- to-Digital Converter (A/D) Module
- 21.0 Comparator Module
- Register 21-1: CMCON: Comparator Control Register
- 21.1 Comparator Configuration
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
- 22.0 Comparator Voltage Reference Module
- 23.0 Low-Voltage Detect
- 24.0 Special Features of the CPU
- 24.1 Configuration Bits
- TABLE 24-1: Configuration Bits and Device IDs
- Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 24-3: config2h: Configuration Register 2 High (Byte Address 300003h)
- Register 24-4: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
- Register 24-5: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
- Register 24-6: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
- Register 24-7: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
- Register 24-8: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
- Register 24-9: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
- Register 24-10: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
- Register 24-11: DEVID1: Device ID Register 1 for PIC18FXX8 Devices (Byte Address 3FFFFEh)
- Register 24-12: DEVID2: Device ID Register 2 for PIC18FXX8 Devices (Byte Address 3FFFFFh)
- 24.2 Watchdog Timer (WDT)
- 24.3 Power-Down Mode (Sleep)
- 24.4 Program Verification and Code Protection
- 24.5 ID Locations
- 24.6 In-Circuit Serial Programming
- 24.7 In-Circuit Debugger
- 24.8 Low-Voltage ICSP Programming
- 24.1 Configuration Bits
- 25.0 Instruction Set Summary
- 26.0 Development Support
- 26.1 MPLAB Integrated Development Environment Software
- 26.2 MPASM Assembler
- 26.3 MPLAB C17 and MPLAB C18 C Compilers
- 26.4 MPLINK Object Linker/ MPLIB Object Librarian
- 26.5 MPLAB C30 C Compiler
- 26.6 MPLAB ASM30 Assembler, Linker and Librarian
- 26.7 MPLAB SIM Software Simulator
- 26.8 MPLAB SIM30 Software Simulator
- 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
- 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
- 26.11 MPLAB ICD 2 In-Circuit Debugger
- 26.12 PRO MATE II Universal Device Programmer
- 26.13 MPLAB PM3 Device Programmer
- 26.14 PICSTART Plus Development Programmer
- 26.15 PICDEM 1 PICmicro Demonstration Board
- 26.16 PICDEM.net Internet/Ethernet Demonstration Board
- 26.17 PICDEM 2 Plus Demonstration Board
- 26.18 PICDEM 3 PIC16C92X Demonstration Board
- 26.19 PICDEM 4 8/14/18-Pin Demonstration Board
- 26.20 PICDEM 17 Demonstration Board
- 26.21 PICDEM 18R PIC18C601/801 Demonstration Board
- 26.22 PICDEM LIN PIC16C43X Demonstration Board
- 26.23 PICkitTM 1 Flash Starter Kit
- 26.24 PICDEM USB PIC16C7X5 Demonstration Board
- 26.25 Evaluation and Programming Tools
- 27.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 27.1 DC Characteristics
- 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
- 27.3 AC (Timing) Characteristics
- 27.3.1 Timing Parameter Symbology
- 27.3.2 Timing Conditions
- 27.3.3 Timing Diagrams and Specifications
- FIGURE 27-6: External Clock Timing
- TABLE 27-6: External Clock Timing Requirements
- TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V)
- FIGURE 27-7: CLKO and I/O Timing
- TABLE 27-8: CLKO and I/O Timing Requirements
- FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 27-9: Brown-out Reset and Low-Voltage Detect Timing
- TABLE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and...
- FIGURE 27-10: Timer0 and Timer1 External Clock Timings
- TABLE 27-10: Timer0 and Timer1 External Clock Requirements
- FIGURE 27-11: Capture/Compare/PWM Timings (CCP1 and ECCP1)
- TABLE 27-11: Capture/Compare/PWM Requirements (CCP1 and ECCP1)
- FIGURE 27-12: Parallel Slave Port Timing (PIC18F248 and PIC18F458)
- TABLE 27-12: Parallel Slave Port Requirements (PIC18F248 and PIC18F458)
- FIGURE 27-13: Example SPI™ Master Mode Timing (CKE=0)
- TABLE 27-13: Example SPI™ Mode Requirements (Master Mode, CKE=0)
- FIGURE 27-14: Example SPI™ Master Mode Timing (CKE=1)
- TABLE 27-14: Example SPI™ Mode Requirements (Master Mode, CKE=1)
- FIGURE 27-15: Example SPI™ Slave Mode Timing (CKE=0)
- TABLE 27-15: Example SPI™ Mode Requirements, Slave Mode Timing (CKE=0)
- FIGURE 27-16: Example SPI™ Slave Mode Timing (CKE=1)
- TABLE 27-16: Example SPI™ Slave Mode Requirements (CKE=1)
- FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing
- TABLE 27-17: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 27-18: I2C™ Bus Data Timing
- TABLE 27-18: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 27-19: Master SSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 27-20: Master SSP I2C™ Bus Data Timing
- TABLE 27-20: Master SSP I2C™ Bus Data Requirements
- FIGURE 27-21: USART Synchronous Transmission (Master/Slave) Timing
- TABLE 27-21: USART Synchronous Transmission Requirements
- FIGURE 27-22: USART Synchronous Receive (Master/Slave) Timing
- TABLE 27-22: USART Synchronous Receive Requirements
- TABLE 27-23: A/D Converter Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
- FIGURE 27-23: A/D Conversion Timing
- TABLE 27-24: A/D Conversion Requirements
- 28.0 DC and AC Characteristics Graphs and Tables
- FIGURE 28-1: Typical Idd vs. Fosc Over Vdd (Hs Mode)
- FIGURE 28-2: Maximum Idd vs. Fosc Over Vdd (Hs Mode)
- FIGURE 28-3: Typical Idd vs. Fosc Over Vdd (HS/PLL Mode)
- FIGURE 28-4: Maximum Idd vs. Fosc Over Vdd (HS/PLL Mode)
- FIGURE 28-5: Typical Idd vs. Fosc Over Vdd (XT Mode)
- FIGURE 28-6: Maximum Idd vs. Fosc Over Vdd (XT Mode)
- FIGURE 28-7: Typical Idd vs. Fosc Over Vdd (LP Mode)
- FIGURE 28-8: Maximum Idd vs. Fosc Over Vdd (LP Mode)
- FIGURE 28-9: Typical Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 28-10: Maximum Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 28-11: Typical and Maximum Idd vs. Vdd (Timer1 as Main Oscillator 32.768kHz, C1 and C2 = ...
- FIGURE 28-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25°C)
- FIGURE 28-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25°C)
- FIGURE 28-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25°C)
- FIGURE 28-15: Ipd vs. Vdd, -40°C to +125°C (Sleep Mode, All Peripherals Disabled)
- FIGURE 28-16: DIbor vs. Vdd Over Temperature (BOR Enabled, Vbor = 2.00-2.16V)
- FIGURE 28-17: Typical and Maximum DItmr1 vs. Vdd Over Temperature (-10°C to +70°C, Timer1 with Os...
- FIGURE 28-18: Typical and Maximum DIwdt vs. Vdd Over Temperature (WDT Enabled)
- FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)
- FIGURE 28-20: DIlvd vs. Vdd Over Temperature (LVD Enabled, Vlvd = 4.5 - 4.78V)
- FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C)
- FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C)
- FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C)
- FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C)
- FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)
- FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40°C to +125°C)
- FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C™ Input, -40°C to +125°C)
- FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40°C to +125°C)
- FIGURE 28-29: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40°C to +125°C)
- 29.0 Packaging Information
- 29.1 Package Marking Information
- 29.1 Package Marking Information (Continued)
- 29.2 Package Details
- 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
- 28-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC)
- 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
- 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
- 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
- Appendix A: Data Sheet Revision History
- Appendix B: Device Differences
- Appendix C: Device Migrations
- Appendix D: Migrating From Other PICmicro® Devices
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- PIC18FXX8 Product Identification System
- Worldwide Sales and Service
© 2006 Microchip Technology Inc. DS41159E-page 315
PIC18FXX8
RRNCF Rotate Right f (no carry)
Syntax: [
label
] RRNCF f [,d [,a]]
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:
RRNCF REG, W
Before Instruction
W=?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: [
label
] SETF f [,a]
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: FFh → f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
SETF REG
Before Instruction
REG = 0x5A
After Instruction
REG = 0xFF