Datasheet

PIC18FXX8
DS41159E-page 248 © 2006 Microchip Technology Inc.
20.5 Use of the ECCP Trigger
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE
bit will be set, starting the A/D conversion and the
Timer1 (or Timer3) counter will be reset to zero. Timer1
(or Timer3) is reset to automatically repeat the A/D
acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done before the “special event
trigger” sets the GO/DONE
bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
FIGURE 20-4: A/D CONVERSION TAD CYCLES
TABLE 20-3: SUMMARY OF A/D REGISTERS
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input
b9
b8
b7 b6
b5
b4
b3 b2
TAD9 TAD10
b1 b0
TCY - TAD
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion Starts
b0
(typically 100 ns)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIR2
—CMIF
(1)
—EEIFBCLIF LVDIF TMR3IF ECCP1IF
(1)
-0-0 0000 -0-0 0000
PIE2
—CMIE
(1)
—EEIEBCLIE LVDIE TMR3IE ECCP1IE
(1)
-0-0 0000 -0-0 0000
IPR2
—CMIP
(1)
—EEIPBCLIP LVDIP TMR3IP ECCP1IP
(1)
-1-1 1111 -1-1 1111
ADRESH A/D Result Register xxxx xxxx uuuu uuuu
ADRESL A/D Result Register xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 0000 00-0
ADCON1 ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
PORTA
— RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000
TRISA
— PORTA Data Direction Register -111 1111 -111 1111
PORTE
— — — — — RE2 RE1 RE0 ---- -xxx ---- -000
LATE
— — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
TRISE
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.