Datasheet

PIC18FXX8
DS41159E-page 242 © 2006 Microchip Technology Inc.
REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 F
OSC/2
0 01 F
OSC/8
0 10 F
OSC/32
0 11 F
RC (clock derived from the internal A/D RC oscillator)
1 00 F
OSC/4
1 01 F
OSC/16
1 10 F
OSC/64
1 11 F
RC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note: Shaded cells indicate channels available only on PIC18F4X8 devices.
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF-C/R
0000
A A AA A A AAVDD VSS 8/0
0001
A A AAVREF+A A A AN3 VSS 7/1
0010
D D DA A A AAVDD VSS 5/0
0011
D D DAVREF+A A A AN3 VSS 4/1
0100
D D DD A D AAVDD VSS 3/0
0101
D D DDVREF+D A A AN3 VSS 2/1
011x
D D DD D D DD — — 0/0
1000
A A AAVREF+VREF-A A AN3 AN2 6/2
1001
D D AA A A AAVDD VSS 6/0
1010
D D AAVREF+A A A AN3 VSS 5/1
1011
D D AAVREF+VREF-A A AN3 AN2 4/2
1100
D D DAVREF+VREF-A A AN3 AN2 3/2
1101
D D DDVREF+VREF-A A AN3 AN2 2/2
1110
D D DD D D DAVDD VSS 1/0
1111
D D DDVREF+VREF-D A AN3 AN2 1/2