Datasheet

© 2006 Microchip Technology Inc. DS41159E-page 211
PIC18FXX8
REGISTER 19-13: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0
RXFUL
(1)
RXM1
(1)
RXM0
(1)
— RXRTRRO FILHIT2 FILHIT1 FILHIT0
bit 7 bit 0
bit 7 RXFUL: Receive Full Status bit
(1)
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note: This bit is set by the CAN module and should be cleared by software after the buffer
is read.
bit 6-5 RXM1:RXM0: Receive Buffer Mode bits
(1)
11 = Receive all messages (including those with errors)
10 = Receive only valid messages with extended identifier
01 = Receive only valid messages with standard identifier
00 = Receive all valid messages
bit 4 Unimplemented: Read as ‘0’
bit 3 RXRTRRO: Receive Remote Transfer Request bit (read-only)
1 = Remote transfer request
0 = No remote transfer request
bit 2-0 FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive
Buffer 1.
111 = Reserved
110 = Reserved
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set
000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON.
Legend:
R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown