PIC18FXX8 Data Sheet 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module © 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18FXX8 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN High-Performance RISC CPU: Advanced Analog Features: • Linear program memory addressing up to 2 Mbytes • Linear data memory addressing to 4 Kbytes • Up to 10 MIPS operation • DC – 40 MHz clock input • 4 MHz-10 MHz oscillator/clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • 8 x 8 Single-Cycle Hardware Multiplier • 10-bit, up to 8-channel Analog-to-Digital Converter
Comparators PIC18FXX8 CCP/ ECCP (PWM) PIC18F248 16K 8192 768 256 22 5 — 1/0 Y Y Y 1/3 PIC18F258 32K 16384 1536 256 22 5 — 1/0 Y Y Y 1/3 PIC18F448 16K 8192 768 256 33 8 2 1/1 Y Y Y 1/3 PIC18F458 32K 16384 1536 256 33 8 2 1/1 Y Y Y 1/3 Program Memory Device Data Memory I/O Flash # Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) 10-bit A/D (ch) MSSP Master I2C™ USART SPI™ Timers 8/16-bit Pin Diagrams PDIP RB7/PGD RB6/PGC RB5/PGM RB4 RB3
PIC18FXX8 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI NC TQFP 1 2 3 4 5 6 7 8 9 10 11 PIC18F448 PIC18F458 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI VSS VDD RE2/AN7/CS/C2OUT RE1/AN6/WR/C1OUT RE0//AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ NC NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP 12 13 14 15 16 17
PIC18FXX8 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 17 3.0 Reset ...........................................................................................
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PIC18FXX8 NOTES: DS41159E-page 6 © 2006 Microchip Technology Inc.
PIC18FXX8 1.0 DEVICE OVERVIEW 2. This document contains device specific information for the following devices: 3. • • • • 4. PIC18F248 PIC18F258 PIC18F448 PIC18F458 These devices are available in 28-pin, 40-pin and 44-pin packages. They are differentiated from each other in four ways: 1. PIC18FX58 devices have twice the Flash program memory and data RAM of PIC18FX48 devices (32 Kbytes and 1536 bytes vs. 16 Kbytes and 768 bytes, respectively).
PIC18FXX8 FIGURE 1-1: PIC18F248/258 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 Data RAM up to 1536 bytes inc/dec logic 21 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 Data Latch Address Latch 21 PCLATU PCLATH PCU PCH PCL Program Counter Program Memory up to 32 Kbytes RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD Address<12> 12 4 BSR Address Latch PORTB 12 31 Level Stack 4 FSR0 Bank0, F FSR1 FSR2 12 Data La
PIC18FXX8 FIGURE 1-2: PIC18F448/458 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 Data RAM up to 1536 Kbytes inc/dec logic 21 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 Data Latch Address Latch 21 PCLATU PCLATH PCU PCH PCL Program Counter Program Memory up to 32 Kbytes RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD 12 4 BSR Address Latch PORTB 12 Address<12> 31 Level Stack 4 FSR0 Bank0, F FSR1 FSR2 12 Data La
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F248/258 MCLR/VPP PIC18F448/458 SPDIP, SOIC PDIP TQFP PLCC 1 1 18 2 Pin Type Buffer Type MCLR I ST VPP P — — — NC — — OSC1/CLKI 9 13 12, 13, 1, 17, 33, 34 28, 40 30 14 OSC1 I CLKI I OSC2/CLKO/RA6 OSC2 10 14 31 CLKO RA6 Legend: TTL ST I P DS41159E-page 10 TTL compatible input Schmitt Trigger input with CMOS levels Input Power Master Clear (input) or programming voltage (output).
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 PIC18F448/458 SPDIP, SOIC PDIP TQFP PLCC 2 2 19 3 Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0/CVREF RA0 AN0 CVREF RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 6 3 4 5 6 20 21 22 23 7 7 24 TTL Analog Analog Digital I/O. Analog input 0. Comparator voltage reference output.
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC PIC18F448/458 PDIP TQFP Pin Type Buffer Type Description PLCC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC PIC18F448/458 PDIP TQFP Pin Type Buffer Type Description PLCC PORTC is a bidirectional I/O port.
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC PIC18F448/458 PDIP TQFP Pin Type Buffer Type Description PLCC PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.
PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 PIC18F448/458 SPDIP, SOIC PDIP TQFP PLCC RE0/AN5/RD RE0 AN5 RD — 8 25 9 RE1/AN6/WR/C1OUT RE1 AN6 WR — Pin Type Buffer Type Description PORTE is a bidirectional I/O port. 9 26 — 10 ST Analog TTL Digital I/O. Analog input 5. Read control for Parallel Slave Port (see WR and CS pins). I/O I I ST Analog TTL O Analog Digital I/O. Analog input 6.
PIC18FXX8 NOTES: DS41159E-page 16 © 2006 Microchip Technology Inc.
PIC18FXX8 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) The PIC18FXX8 can be operated in one of eight oscillator modes, programmable by three configuration bits (FOSC2, FOSC1 and FOSC0). 1. 2. 3. 4. LP XT HS HS4 5. 6. RC RCIO 7. 8. EC ECIO 2.
PIC18FXX8 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type Crystal Freq LP 32.0 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF XT HS Cap. Range C1 Cap. Range C2 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes on this page. 2.
PIC18FXX8 2.4 FIGURE 2-4: External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic.
PIC18FXX8 2.6 2.6.1 Oscillator Switching Feature The PIC18FXX8 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. For the PIC18FXX8 devices, this alternate clock source is the Timer1 oscillator. If a low-frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a Low-Power Execution mode.
PIC18FXX8 2.6.2 OSCILLATOR TRANSITIONS The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. The PIC18FXX8 devices contain circuitry to prevent “glitches” when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to.
PIC18FXX8 If the main oscillator is configured for HS4 (PLL) mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9. FIGURE 2-9: If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out.
PIC18FXX8 2.7 Effects of Sleep Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, Sleep mode achieves the lowest current consumption of the device (only leakage currents).
PIC18FXX8 NOTES: DS41159E-page 24 © 2006 Microchip Technology Inc.
PIC18FXX8 3.0 RESET The PIC18FXX8 differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset during normal operation Programmable Brown-out Reset (PBOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets.
PIC18FXX8 3.1 Power-on Reset (POR) 3.3 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when a VDD rise is detected. To take advantage of the POR circuitry, connect the MCLR pin directly (or through a resistor) to VDD. This eliminates external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (refer to parameter D004). For a slow rise time, see Figure 3-2.
PIC18FXX8 3.7 Time-out Sequence Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18FXX8 device operating in parallel. On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired, then OST is activated.
PIC18FXX8 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 3-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 3-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41159E-page 28 © 2006 Microchip Technology Inc.
PIC18FXX8 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2006 Microchip Technology Inc.
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2X8 PIC18F4X8 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---u
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H PIC18F2X8 PIC18F4X8 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC2 PIC18F2X8 PIC18F4X
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADCON1 PIC18F2X8 PIC18F4X8 00-- 0000 00-- 0000 uu-- uuuu CCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2X8 PIC18F4X8 --00 0000 --00 0000 --uu uuuu ECCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuu
PIC18FXX8 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TRISE PIC18F2X8 PIC18F4X8 0000 -111 0000 -111 uuuu -uuu TRISD PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 (5) uuuu uuuu -111 1111 -uuu uuuu(5) ---- -xxx ----
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt RXB0DLC PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx u
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON PIC18F2X8 PIC18F4X8 -000 0-00 -000 0-00 -uuu u-uu TXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uu
PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt RXM1SIDL PIC18F2X8 PIC18F4X8 xxx- --xx uuu- --uu uuu- --uu RXM1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL PIC18F2X8 PIC18F4X8 xxx- --xx
PIC18FXX8 4.0 MEMORY ORGANIZATION There are three memory blocks in Enhanced MCU devices. These memory blocks are: • Enhanced Flash Program Memory • Data Memory • EEPROM Data Memory 4.1.1 Data and program memory use separate busses, which allows concurrent access of these blocks. Additional detailed information on data EEPROM and Flash program memory is provided in Section 5.0 “Data EEPROM Memory” and Section 6.0 “Flash Program Memory”, respectively. 4.
PIC18FXX8 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a PUSH, CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN instructions.
PIC18FXX8 REGISTER 4-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note: Bit 7 and bit 6 need to be cleared fo
PIC18FXX8 4.2.3 PUSH AND POP INSTRUCTIONS Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack.
PIC18FXX8 4.5 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-4.
PIC18FXX8 EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW 1. MOVLW 55h TCY0 TCY1 Fetch 1 Execute 1 Fetch 2 2. MOVWF PORTB TCY3 TCY5 Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush Fetch SUB_1 5. Instruction @ address SUB_1 Note: TCY4 Execute 2 Fetch 3 3. BRA SUB_1 4. BSF TCY2 Execute SUB_1 All instructions are single cycle, except for any program branches.
PIC18FXX8 4.7.1 TWO-WORD INSTRUCTIONS The PIC18FXX8 devices have 4 two-word instructions: MOVFF, CALL, GOTO and LFSR. The 4 Most Significant bits of the second word are set to ‘1’s and indicate a special NOP instruction. The lower 12 bits of the second word contain the data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP.
PIC18FXX8 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-6 shows the data memory organization for the PIC18FXX8 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented.
PIC18FXX8 FIGURE 4-5: DATA MEMORY MAP FOR PIC18F248/448 BSR<3:0> = 0000 = 0001 = 0010 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 1FFh 200h FFh 00h Bank 2 GPR 300h FFh = 0011 = 1110 000h 05Fh 060h 0FFh 100h Bank 3 to Bank 14 Access Bank 00h Access Bank Low (GPR) 5Fh 60h Access Bank High (SFR) FFh When a = 0, the BSR is ignored and the Access Bank is used. Unused Read ‘00h’ The first 96 bytes are general purpose RAM (from Bank 0).
PIC18FXX8 FIGURE 4-6: DATA MEMORY MAP FOR PIC18F258/458 BSR<3:0> = 0000 = 0001 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 FFh 00h = 0010 Bank 2 = 0011 1FFh 200h GPR 2FFh 300h FFh 00h Bank 3 GPR 3FFh 400h FFh = 0100 = 0101 000h 05Fh 060h 0FFh 100h Bank 4 Access Bank GPR 4FFh 500h 00h GPR Bank 5 FFh 5FFh 600h Access Bank low (GPR) Access Bank high (SFR) 00h 5Fh 60h FFh = 0110 = 1110 Bank 6 to Bank 14 When a = 0, the BSR is ignored and the Access Bank is used.
PIC18FXX8 TABLE 4-1: Address SPECIAL FUNCTION REGISTER MAP Name Address FFFh TOSU FDFh Name INDF2(2) Address Name Address FBFh CCPR1H (2) Name F9Fh IPR1 FFEh TOSH FDEh POSTINC2 FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(2) FBCh ECCPR1H(5) F9Ch FFBh PCLATU (2) FBBh ECCPR1L(5) F9Bh — F9Ah — F99h — F98h — F97h — FDBh PLUSW2 FFAh PCLATH FDAh FSR2H FBAh ECCP1CON FF9h PCL FD9h FSR2L FB9h — — (5) FF8h TBLPTRU FD8h
PIC18FXX8 TABLE 4-1: Address SPECIAL FUNCTION REGISTER MAP (CONTINUED) Name F7Fh — Address F5Fh Name Address — F3Fh (4) Name Address — Name F1Fh RXM1EIDL F3Eh CANSTATRO3 (4) F7Eh — F5Eh CANSTATRO1 F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F1Eh RXM1EIDH F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h — F58h RXB1D2 F38h TXB1
PIC18FXX8 TABLE 4-2: File Name REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on Page: ---0 0000 30, 38 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 30, 38 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 30, 38 Return Stack Pointer 00-0 0000 30, 39 Holding Register for PC<20:16> ---0 0000 30, 40 TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(2) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR PCLATH Holding Register for
PIC18FXX8 TABLE 4-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: TMR1H Timer1 Register High Byte xxxx xxxx 31, 116 TMR1L Timer1 Register Low Byte xxxx xxxx 31, 116 T1CON RD16 0-00 0000 31, 113 TMR2 Timer2 Register 0000 0000 31, 118 PR2 Timer2 Period Register 1111 1111 31, 118 -000 0000 31, 117 T2CON — — TOUTPS3 T1CKPS1 TOUTPS2 T1CKPS0 TOUTPS1 T1OSCEN TOUTPS0 T1SYNC TMR2ON TMR1CS T
PIC18FXX8 TABLE 4-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 32, 88 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 32, 82 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE IBF OBF IBOV PSPMODE — TRISE(1) Data Direction bits for PORTE(1) 0000 0000 32, 85 0000 -111 33, 105 TRISD(1)
PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Bit 0 Value on POR, BOR Details on Page: ICODE0 — xxx- xxx- 33, 202 RXB1D71 RXB1D70 xxxx xxxx 34, 214 RXB1D61 RXB1D60 xxxx xxxx 34, 214 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 34, 214 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 34, 214 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 34, 214 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 34, 214 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10
PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 CANSTATRO4 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 35, 208 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 35, 208 TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52
PIC18FXX8 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler are also useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18FXX8 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not fixed. A SFR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-8 shows the operation of indirect addressing.
PIC18FXX8 FIGURE 4-8: INDIRECT ADDRESSING Indirect Addressing FSR Register 11 8 7 FSRnH 0 FSRnL Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-1. DS41159E-page 56 © 2006 Microchip Technology Inc.
PIC18FXX8 4.13 Status Register The Status register, shown in Register 4-2, contains the arithmetic status of the ALU. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18FXX8 4.14 RCON Register Note 1: If the BOREN configuration bit is set, BOR is ‘1’ on Power-on Reset. If the BOREN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a “don’t care” and is not necessarily predictable if the brownout circuit is disabled (the BOREN configuration bit is clear). BOR must then be set by the user and checked on subsequent Resets to see if it is clear, indicating a brown-out has occurred.
PIC18FXX8 5.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write.
PIC18FXX8 REGISTER 5-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable b
PIC18FXX8 5.3 Reading the Data EEPROM Memory 5.4 To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD and CFGS control bits (EECON1<7:6>) and then set control bit RD (EECON1<0>). The data is available in the very next instruction cycle of the EEDATA register; therefore, it can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation).
PIC18FXX8 5.5 Write Verify 5.7 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Operation During Code-Protect Data EEPROM memory has its own code-protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled.
PIC18FXX8 TABLE 5-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Value on all other Resets Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON GIE/GIEH PEIE/GIEL TMR0IE EEADR EEPROM Address Register xxxx xxxx uuuu uuuu EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu EECON2 EEPROM Control Register 2 (not a physical register) — CFGS — FREE WRERR WREN IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP
PIC18FXX8 NOTES: DS41159E-page 64 © 2006 Microchip Technology Inc.
PIC18FXX8 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time.
PIC18FXX8 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. 6.
PIC18FXX8 REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable b
PIC18FXX8 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT.
PIC18FXX8 6.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 6-4: The internal program memory is typically organized by words.
PIC18FXX8 6.4 Erasing Flash Program Memory 6.4.1 The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18FXX8 6.5 6.5.1 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation.
PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER high (BUFFER_ADDR) FSR0H low (BUFFER_ADDR) FSR0L upper (CODE_ADDR) TBLPTRU high (CODE_ADDR) TBLPTRH low (CODE_ADDR) TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point t
PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) WRITE_WORD_TO_HREGS MOVFW POSTINC0, W MOVWF TABLAT TBLWT+* DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full ; ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory disable interrupts write 55h PROGRAM_MEMORY Required Sequence 6.5.
PIC18FXX8 TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Value on: POR, BOR Value on all other Resets --00 0000 --00 0000 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH 0000 000x 0000 000u EECON2 EEPROM Control Register 2 (not a physical register) — — Name Bit 7 Bit 6 Bit 5 TBLPTRU — —
PIC18FXX8 7.0 8 x 8 HARDWARE MULTIPLIER 7.1 Introduction 7.2 Example 7-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX8 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18FXX8 Example 7-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
PIC18FXX8 8.0 INTERRUPTS The PIC18FXX8 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are 13 registers that are used to control interrupt operation.
PIC18FXX8 FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Sleep mode INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to Location 0008h GIE/GIEH TMR1IF TMR1IE TMR1IP IPEN IPEN GIEL/PEIE XXXXIF XXXXIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit
PIC18FXX8 8.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. The INTCON registers are readable and writable registers which contain various enable, priority and flag bits.
PIC18FXX8 REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 RBPU bit 7 R/W-1 R/W-1 INTEDG0 INTEDG1 U-0 U-0 R/W-1 U-0 — — TMR0IP — bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edg
PIC18FXX8 REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 extern
PIC18FXX8 8.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON register). The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts (Register 8-4 through Register 8-6). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3).
PIC18FXX8 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF(1) — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit(1) 1 = Comparator input has changed 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = Write operation is complete (must be cleared in software) 0 = Write
PIC18FXX8 REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF bit 7 bit 0 bit 7 IRXIF: Invalid Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = An invalid message has not occurred on the CAN bus bit 6 WAKIF: Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = Activity on the CAN bus has not occurre
PIC18FXX8 8.3 PIE Registers The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts (Register 8-7 through Register 8-9). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN is clear, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18FXX8 REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE(1) — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: EEPROM Write Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = E
PIC18FXX8 REGISTER 8-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 bit 7 IRXIE: Invalid CAN Message Received Interrupt Enable bit 1 = Enables the invalid CAN message received interrupt 0 = Disables the invalid CAN message received interrupt bit 6 WAKIE: Bus Activity Wake-up Interrupt Enable bit 1 = Enables the bus activity wake-up interrupt 0 = Disables the bus activity wa
PIC18FXX8 8.4 IPR Registers The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set.
PIC18FXX8 REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP(1) — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: EEPROM Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low
PIC18FXX8 REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: Invalid Message Received Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: Transmit Buffe
PIC18FXX8 8.5 RCON Register The Reset Control (RCON) register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”.
PIC18FXX8 8.6 INT Interrupts 8.8 External interrupts on the RB0/INT0, RB1/INT1 and RB2/CANTX/INT2 pins are edge triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE.
PIC18FXX8 9.0 I/O PORTS Depending on the device selected, there are up to five general purpose I/O ports available on PIC18FXX8 devices. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PIC18FXX8 FIGURE 9-1: RA3:RA0 AND RA5 PINS BLOCK DIAGRAM FIGURE 9-2: RD LATA Data Bus WR LATA or WR PORTA RA4/T0CKI PIN BLOCK DIAGRAM RD LATA Q D Data Bus VDD CK Q WR LATA or WR PORTA P Data Latch Q D CK Q N I/O pin(1) Data Latch Q D WR TRISA Analog Input Mode CK I/O pin(1) N Q WR TRISA VSS TRIS Latch D Q CK Q VSS TRIS Latch RD TRISA Q RD TRISA TTL Input Buffer D TTL Input Buffer Schmitt Trigger Input Buffer Q EN D EN RD PORTA RD PORTA TMR0 Clock Input SS Input (RA
PIC18FXX8 TABLE 9-1: PORTA FUNCTIONS Name RA0/AN0/CVREF Bit# Buffer bit 0 TTL Function Input/output, analog input or analog comparator voltage reference output. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output, analog input or VREF-. TTL Input/output, analog input or VREF+. RA3/AN3/VREF+ bit 3 RA4/T0CKI bit 4 RA5/AN4/SS/LVDIN bit 5 TTL Input/output, analog input, slave select input for synchronous serial port or Low-Voltage Detect input.
PIC18FXX8 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18FXX8 FIGURE 9-4: RB7:RB4 PINS BLOCK DIAGRAM FIGURE 9-5: RB1:RB0 PINS BLOCK DIAGRAM VDD VDD RBPU(2) Data Bus WR LATB or WR PORTB Weak P Pull-up Data Bus Q I/O pin(1) CK TTL Input Buffer CK D Q I/O pin(1) WR Port TRIS Latch D Q WR TRISB Weak P Pull-up Data Latch Data Latch D RBPU(2) CK TRIS Latch D Q ST Buffer WR TRIS TTL Input Buffer CK RD TRISB RD LATB RD TRIS Latch Q D Q D RD PORTB EN Q1 EN Set RBIF RD Port Q From other RB7:RB4 pins D EN Q3 RBx/INTx Schmitt Trigger
PIC18FXX8 FIGURE 9-6: RB2/CANTX/INT2 PIN BLOCK DIAGRAM OPMODE2:OPMODE0 = 000 ENDRHI CANTX 0 RD LATB VDD Data Latch Data Bus D Q WR PORTB or WR LATB CK Q 1 P TRIS Latch Q D RB2/CANTX/ INT2 pin(1) N WR TRISB CK Q VSS Schmitt Trigger RD TRISB Q D EN RD PORTB Note 1: I/O pin has diode protection to VDD and VSS.
PIC18FXX8 TABLE 9-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. RB2/CANTX/ INT2 bit 2 TTL/ST(1) Input/output pin, CAN bus transmit pin or external interrupt 2 input. Internal software programmable weak pull-up.
PIC18FXX8 9.3 PORTC, TRISC and LATC Registers while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode).
PIC18FXX8 TABLE 9-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI bit 1 ST Input/output port pin or Timer1 oscillator input. RC2/CCP1 bit 2 ST Input/output port pin or Capture 1 input/Compare 1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST Input/output port pin or synchronous serial clock for SPI™/I2C™.
PIC18FXX8 9.4 Note: PORTD, TRISD and LATD Registers This port is only available on the PIC18F448 and PIC18F458. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register for the port is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18FXX8 TABLE 9-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0/C1IN+ bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or C1IN+ comparator input. RD1/PSP1/C1IN- bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or C1IN- comparator input. RD2/PSP2/C2IN+ bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or C2IN+ comparator input.
PIC18FXX8 9.5 PORTE, TRISE and LATE Registers Note: When the Parallel Slave Port is active, the PORTE pins function as its control inputs. For additional details, refer to Section 10.0 “Parallel Slave Port”. This port is only available on the PIC18F448 and PIC18F458. PORTE pins are also multiplexed with inputs for the A/D converter and outputs for the analog comparators. When selected as an analog input, these pins will read as ‘0’s.
PIC18FXX8 REGISTER 9-1: TRISE REGISTER R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write
PIC18FXX8 TABLE 9-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/AN5/RD bit 0 ST/TTL(1) Input/output port pin, analog input or read control input in Parallel Slave Port mode. RE1/AN6/WR/C1OUT bit 1 ST/TTL(1) Input/output port pin, analog input, write control input in Parallel Slave Port mode or Comparator 1 output. RE2/AN7/CS/C2OUT bit 2 ST/TTL(1) Input/output port pin, analog input, chip select control input in Parallel Slave Port mode or Comparator 2 output.
PIC18FXX8 10.0 PARALLEL SLAVE PORT Note: FIGURE 10-1: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is only available on PIC18F4X8 devices. One bit of PORTD In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 9-1). Setting control bit PSPMODE (TRISE<4>) enables PSP operation.
PIC18FXX8 FIGURE 10-3: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF TABLE 10-1: Name REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE LATE TRISE INTCON
PIC18FXX8 11.0 TIMER0 MODULE Register 11-1 shows the Timer0 Control register (T0CON).
PIC18FXX8 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus 1 8 RA4/T0CKI pin(2) T0SE 1 FOSC/4 Sync with Internal Clocks 0 Programmable Prescaler TMR0L 0 (2 TCY Delay) 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS (1) Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS.
PIC18FXX8 11.1 11.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles.
PIC18FXX8 NOTES: DS41159E-page 112 © 2006 Microchip Technology Inc.
PIC18FXX8 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger REGISTER 12-1: Register 12-1 shows the Timer1 Control register.
PIC18FXX8 12.1 Timer1 Operation When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.
PIC18FXX8 12.2 Timer1 Oscillator 12.4 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON register). The oscillator is a low-power oscillator rated up to 50 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.
PIC18FXX8 TABLE 12-2: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 INTCON
PIC18FXX8 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Register 13-1 shows the Timer2 Control register.
PIC18FXX8 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is a clock input to the Synchronous Serial Port module which optionally uses it to generate the shift clock.
PIC18FXX8 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP1 and ECCP1 clock source.
PIC18FXX8 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.
PIC18FXX8 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN bit (T1CON register). The oscillator is a low-power oscillator rated up to 50 kHz. Refer to Section 12.0 “Timer1 Module” for Timer1 oscillator details. 14.3 If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3.
PIC18FXX8 NOTES: DS41159E-page 122 © 2006 Microchip Technology Inc.
PIC18FXX8 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES module has a Capture special event trigger that can be used as a message received time-stamp for the CAN module (refer to Section 19.0 “CAN Module” for CAN operation) which the ECCP module does not. The ECCP module, on the other hand, has Enhanced PWM functionality and auto-shutdown capability. Aside from these, the operation of the module described in this section is the same as the ECCP.
PIC18FXX8 15.1 CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR registers), is set. It must be cleared in software.
PIC18FXX8 15.2.3 SOFTWARE INTERRUPT 15.2.5 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE registers) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in operating mode. 15.2.4 CCP1 PRESCALER There are four prescaler settings specified by bits CCP1M3:CCP1M0. Whenever the CCP1 module is turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared.
PIC18FXX8 15.3 15.3.2 Compare Mode In Compare mode, the 16-bit CCPR1 and ECCPR1 register value is constantly compared against either the TMR1 register pair value or the TMR3 register pair value. When a match occurs, the CCP1 pin can have one of the following actions: • • • • Driven high Driven low Toggle output (high-to-low or low-to-high) Remains unchanged CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the appropriate TRISC bit.
PIC18FXX8 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on all other Resets Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TM
PIC18FXX8 15.4 15.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. PWM PERIOD The PWM period is specified by writing to the PR2 register.
PIC18FXX8 15.4.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 15-3: 1. F OSC log ⎛ ---------------⎞ ⎝ F PWM⎠ PWM Resolution (max) = -----------------------------bits log ( 2 ) 2. 3. Note: 4. If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. TABLE 15-4: SETUP FOR PWM OPERATION 5.
PIC18FXX8 NOTES: DS41159E-page 130 © 2006 Microchip Technology Inc.
PIC18FXX8 16.0 Note: ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The ECCP (Enhanced Capture/Compare/ PWM) module is only available on PIC18F448 and PIC18F458 devices. This module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. REGISTER 16-1: bit 5-4 bit 3-0 The control register Register 16-1.
PIC18FXX8 16.1 ECCP1 Module Enhanced Capture/Compare/PWM Register 1 (ECCPR1) is comprised of two 8-bit registers: ECCPR1L (low byte) and ECCPR1H (high byte). The ECCP1CON register controls the operation of ECCP1; the additional registers, ECCPAS and ECCP1DEL, control Enhanced PWM specific features. All registers are readable and writable. Table 16-1 shows the timer resources for the ECCP module modes. Table 16-2 describes the interactions of the ECCP module with the standard CCP module.
PIC18FXX8 16.2 Capture Mode 16.3 The Capture mode of the ECCP module is virtually identical in operation to that of the standard CCP module as discussed in Section 15.1 “CCP1 Module”. The differences are in the registers and port pins involved: Compare Mode The Compare mode of the ECCP module is virtually identical in operation to that of the standard CCP module as discussed in Section 15.2 “Capture Mode”. The differences are in the registers and port pins as described in Section 16.2 “Capture Mode”.
PIC18FXX8 16.4 Standard PWM Mode Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when the assigned timer resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first).
PIC18FXX8 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS 0 ECCP1CON <7:6> SIGNAL PR2 + 1 Duty Cycle Period P1A Modulated, Active-High 00 P1A Modulated, Active-Low P1A Modulated, Active-High P1A Modulated, Active-Low 10 Delay Delay P1B Modulated, Active-High P1B Modulated, Active-Low P1A Active, Active-High P1A Active, Active-Low P1B Inactive, Active-High P1B Inactive, Active-Low 01 P1C Inactive, Active-High P1C Inactive, Active-Low P1D Modulated, Active-High P1D Modulated, Active-Low P1A Inactive, Active-Hi
PIC18FXX8 16.5.2 HALF-BRIDGE MODE FIGURE 16-3: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The RD4/PSP4/ ECCP1/P1A pin has the PWM output signal, while the RD5/PSP5/P1B pin has the complementary PWM output signal (Figure 16-3). This mode can be used for half-bridge applications, as shown in Figure 16-4, or for full-bridge applications where four power switches are being modulated with two PWM signals.
PIC18FXX8 16.5.3 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RD4/PSP4/ECCP1/P1A is continuously active and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continuously active and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-5. FIGURE 16-5: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4:7> data latches.
PIC18FXX8 FIGURE 16-6: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F448/458 FET Driver QB QD FET Driver P1D + Load P1C FET Driver P1B FET Driver QA QC VP1A 16.5.3.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the ECCP1CON register allows the user to control the forward/reverse direction. When the application firmware changes this direction control bit, the ECCP1 module will assume the new direction on the next PWM cycle.
PIC18FXX8 FIGURE 16-7: PWM DIRECTION CHANGE Period(1) SIGNAL Period DC P1A (Active-High) P1B (Active-High) P1C (Active-High) (2) P1D (Active-High) Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM cycle. 2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler value earlier when changing direction. The modulated P1B and P1D signals are inactive at this time.
PIC18FXX8 16.5.4 PROGRAMMABLE DEAD-BAND DELAY In half-bridge or full-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require longer time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches will be on for a short period of time until one switch completely turns off.
PIC18FXX8 16.5.8 SETUP FOR PWM OPERATION 2. The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM module: a) Disable the ECCP1/P1A, P1B, P1C and/or P1D outputs by setting the respective TRISD bits. b) Set the PWM period by loading the PR2 register. c) Set the PWM duty cycle by loading the ECCPR1L register and ECCP1CON<5:4> bits. d) Configure the ECCP1 module for the desired PWM operation by loading the ECCP1CON register with the appropriate value.
PIC18FXX8 16.6 Enhanced CCP Auto-Shutdown When the ECCP is programmed for any of the PWM modes, the output pins associated with its function may be configured for auto-shutdown. Auto-shutdown allows the internal output of either of the two comparator modules, or the external interrupt 0, to asynchronously disable the ECCP output pins. Thus, an external analog or digital event can discontinue an ECCP sequence.
PIC18FXX8 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18FXX8 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18FXX8 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still hol
PIC18FXX8 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18FXX8 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then, set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18FXX8 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18FXX8 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC18FXX8 FIGURE 17-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2↓ SSPSR to SSPBUF FIGURE 17-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit 5 bit 4 bit
PIC18FXX8 17.3.8 SLEEP OPERATION 17.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 17-1: In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device.
PIC18FXX8 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18FXX8 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Mast
PIC18FXX8 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmit
PIC18FXX8 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slav
PIC18FXX8 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18FXX8 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte.
DS41159E-page 158 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
© 2006 Microchip Technology Inc.
DS41159E-page 160 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in software
© 2006 Microchip Technology Inc.
PIC18FXX8 17.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
PIC18FXX8 17.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to ‘0’. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not FIGURE 17-12: assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS41159E-page 164 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs
© 2006 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18FXX8 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18FXX8 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18FXX8 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition, or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
PIC18FXX8 17.4.7 BAUD RATE GENERATOR 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18FXX8 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18FXX8 17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC18FXX8 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC18FXX8 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106).
DS41159E-page 174 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from SSP interrupt 2 D6 Transmitting Da
© 2006 Microchip Technology Inc.
PIC18FXX8 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18FXX8 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA by letting SDA float high and another master asserts a ‘0’.
PIC18FXX8 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). b) During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
PIC18FXX8 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18FXX8 17.4.17.2 Bus Collision During a Repeated Start Condition counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
PIC18FXX8 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31).
PIC18FXX8 NOTES: DS41159E-page 182 © 2006 Microchip Technology Inc.
PIC18FXX8 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex). The SPEN (RCSTA register) and the TRISC<7> bits have to be set and the TRISC<6> bit must be cleared in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
PIC18FXX8 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC18FXX8 18.1 USART Baud Rate Generator (BRG) Example 18-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free running, 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA register) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18FXX8 TABLE 18-3: BAUD RATE (Kbps) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz SPBRG value (decimal) 33 MHz SPBRG value (decimal) 25 MHz SPBRG value (decimal) 20 MHz SPBRG value (decimal) KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.
PIC18FXX8 TABLE 18-4: BAUD RATE (Kbps) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz SPBRG value (decimal) 33 MHz SPBRG value (decimal) 25 MHz SPBRG value (decimal) 20 MHz SPBRG value (decimal) KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR 0.3 NA - - NA - - NA - - NA - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 - 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.
PIC18FXX8 TABLE 18-5: BAUD RATE (Kbps) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz KBAUD % ERROR 0.3 NA - 1.2 NA - 2.4 NA 9.6 SPBRG value (decimal) 33 MHz SPBRG value (decimal) 25 MHz - NA - - NA - - - NA 9.60 -0.07 214 129 19.28 +0.39 32 76.39 -0.54 25 98.21 +2.31 20 MHz SPBRG value (decimal) KBAUD - NA - - NA - - - NA NA - - 19.2 19.23 +0.16 76.8 75.76 -1.36 96 96.15 +0.16 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.
PIC18FXX8 18.2 USART Asynchronous Mode interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1 register). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicated the status of the TXREG register, another bit, TRMT (TXSTA register), shows the status of the TSR register.
PIC18FXX8 FIGURE 18-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) Word 2 Start bit TRMT bit (Transmit Shift Reg.
PIC18FXX8 18.2.2 USART ASYNCHRONOUS RECEIVER 18.2.3 The receiver block diagram is shown in Figure 18-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18FXX8 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX (pin) bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Start bit Stop bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18FXX8 18.3 USART Synchronous Master Mode software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA register), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty.
PIC18FXX8 FIGURE 18-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 7 bit 0 bit 1 bit 7 Word 2 Word 1 RC6/TX/CK pin Write to TXREG Reg Write Word 1 TXIF bit (Interrupt Flag) Write Word 2 TRMT bit TRMT TXEN bit ‘1’ ‘1’ Note: Sync Master mode; SPBRG = 0; continuous transmission of two 8-bit words.
PIC18FXX8 18.3.2 USART SYNCHRONOUS MASTER RECEPTION Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.1 “USART Baud Rate Generator (BRG)”). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN.
PIC18FXX8 18.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in that the shift clock is supplied externally at the RC6/ TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit CSRC (TXSTA register). 18.4.
PIC18FXX8 TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111
PIC18FXX8 NOTES: DS41159E-page 198 © 2006 Microchip Technology Inc.
PIC18FXX8 19.0 CAN MODULE 19.1 Overview The Controller Area Network (CAN) module is a serial interface, useful for communicating with other peripherals or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The CAN module is a communication controller, implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol.
PIC18FXX8 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS Accept TXREQ TXABT TXLARB TXERR TXBUFF TXREQ TXABT TXLARB TXERR TXBUFF Message Request TXREQ TXABT TXLARB TXERR TXBUFF Acceptance Mask RXM1 Acceptance Filter RXM2 TXB0 MESSAGE Accept TXB1 MESSAGE Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 RXB0 RXB1 TXB2 MESSAGE Message Queue Control Identifier Transmit Byte Sequencer
PIC18FXX8 19.2 Note: 19.2.1 CAN Module Registers Not all CAN registers are available in the Access Bank. The registers described in this section control the overall operation of the CAN module and show its operational status. There are many control and data registers associated with the CAN module.
PIC18FXX8 REGISTER 19-2: CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 OPMODE2 OPMODE1 OPMODE0 U-0 R-0 R-0 R-0 U-0 — ICODE2 ICODE1 ICODE0 — bit 7 bit 7-5 bit 0 OPMODE2:OPMODE0: Operation Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable mode 000 = Normal mode Note: Before the device goes into Sleep mode, select Disable mode.
PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.
PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) RXB0Interrupt BCF PIR3, RXB0IF GOTO AccessBuffer ; Clear the interrupt flag AccessBuffer ; This is either TX or RX interrupt ; Copy CANCON.ICODE bits to CANSTAT.WIN bits MOVF CANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW b’11110001’ ; Use previously saved CANCON value to ; make sure same value.
PIC18FXX8 REGISTER 19-3: COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 RXB0OVFL RXB1OVFL R-0 R-0 R-0 TXBO TXBP RXBP R-0 R-0 TXWARN RXWARN bit 7 R-0 EWARN bit 0 bit 7 RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed bit 6 RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit Error Counter > 255 0 = Transmit Error Cou
PIC18FXX8 19.2.2 CAN TRANSMIT BUFFER REGISTERS This section describes the CAN Transmit Buffer registers and their associated control registers.
PIC18FXX8 REGISTER 19-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits if EXIDE = 0 (TXBnSID Register) or Extended Identifier bits EID28:EID21 if EXIDE = 1 Legend: REGISTER 19-6: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is u
PIC18FXX8 REGISTER 19-8: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER, LOW BYTE REGISTERS R/W-x EID7 bit 7 bit 7-0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 EID7:EID0: Extended Identifier bits Legend: REGISTER 19-9: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PIC18FXX8 REGISTER 19-10: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmission Frame Remote Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved
PIC18FXX8 19.2.3 CAN RECEIVE BUFFER REGISTERS This section shows the Receive Buffer registers with their associated control registers.
PIC18FXX8 REGISTER 19-13: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0 RXFUL(1) RXM1(1) RXM0(1) — RXRTRRO FILHIT2 FILHIT1 FILHIT0 bit 7 bit 7 bit 0 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read.
PIC18FXX8 REGISTER 19-14: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits if EXID = 0 (RXBnSIDL Register) or Extended Identifier bits EID28:EID21 if EXID = 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19
PIC18FXX8 REGISTER 19-17: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 7-0 bit 0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-18: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS U-0 R/W-x R/W-x R/W-x R/W
PIC18FXX8 REGISTER 19-19: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 7-0 bit 0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7.
PIC18FXX8 19.2.3.1 Message Acceptance Filters and Masks This subsection describes the message acceptance filters and masks for the CAN receive buffers.
PIC18FXX8 REGISTER 19-23: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 7-0 bit 0 EID15:EID8: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-24: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIE
PIC18FXX8 REGISTER 19-26: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK, LOW BYTE REGISTERS R/W-x R/W-x R/W-x U-0 U-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — — — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18 bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set
PIC18FXX8 19.2.4 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers.
PIC18FXX8 REGISTER 19-30: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 SEG2PHTS SAM R/W-0 R/W-0 R/W-0 R/W-0 SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 R/W-0 R/W-0 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-
PIC18FXX8 REGISTER 19-31: BRGCON3: BAUD RATE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 — WAKFIL — — — R/W-0 R/W-0 R/W-0 SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 Time = 8 x TQ 110 = Phase Se
PIC18FXX8 19.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller.
PIC18FXX8 19.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 8.0 “Interrupts”. They are duplicated here for convenience.
PIC18FXX8 REGISTER 19-34: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5
PIC18FXX8 REGISTER 19-35: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: CAN Tr
PIC18FXX8 TABLE 19-1: Address CAN CONTROLLER REGISTER MAP Name F7Fh Address — F5Fh Name Address — F7Eh — F5Eh CANSTATRO1 F7Dh — F5Dh F7Ch — F7Bh — F7Ah F79h F3Fh (2) Name Address — F3Eh CANSTATRO3 (2) Name F1Fh RXM1EIDL F1Eh RXM1EIDH TXB1D7 F1Dh RXM1SIDL F3Ch TXB1D6 F1Ch RXM1SIDH F3Bh TXB1D5 F1Bh RXM0EIDL RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH RXB1D3 F39h TXB1D3 F19h RXM0SIDL F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL
PIC18FXX8 19.3 CAN Modes of Operation The PIC18FXX8 has six main modes of operation: • • • • • • Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>); Error Recognition is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits.
PIC18FXX8 19.3.5 LOOPBACK MODE This mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus. This mode can be used in system development and testing. In this mode, the ACK bit is ignored and the device will allow incoming messages from itself, just as if they were coming from another node.
PIC18FXX8 19.4.3 INITIATING TRANSMISSION To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. Setting the TXREQ bit does not initiate a message transmission; it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest priority message that is ready.
PIC18FXX8 FIGURE 19-3: INTERNAL TRANSMIT MESSAGE FLOWCHART Start The message transmission sequence begins when the device determines that the TXREQ for any of the transmit registers has been set. Are any TXREQ bits = 1? No Clearing the TXREQ bit while it is set, or setting the ABAT bit before the message has started transmission, will abort the message.
PIC18FXX8 19.5 19.5.1 Message Reception RECEIVE MESSAGE BUFFERING The PIC18FXX8 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) which acts as a third receive buffer (see Figure 19-4). 19.5.2 RECEIVE BUFFERS Of the three receive buffers, the MAB is always committed to receiving the next message from the bus.
PIC18FXX8 FIGURE 19-5: INTERNAL MESSAGE RECEPTION FLOWCHART Start Detect Start of Message? No Yes Begin Loading Message into Message Assembly Buffer (MAB) Generate Error Frame Valid Message Received? No Yes Yes, meets criteria Yes, meets criteria Message for RXB1 for RXBO Identifier meets a Filter Criteria? No Go to Start The RXFUL bit determines if the receive register is empty and able to accept a new message. The RXB0DBEN bit determines if RXB0 can rollover into RXB1 if it is full.
PIC18FXX8 19.6 Message Acceptance Filters and Masks For RXB1, the RXB1CON register contains the FILHIT<2:0> bits. They are coded as follows: The message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers. Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values.
PIC18FXX8 19.7 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitters clock.
PIC18FXX8 19.7.1 TIME QUANTA 19.7.2 SYNCHRONIZATION SEGMENT As already mentioned, the time quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the nominal bit rate is shown in Example 19-2. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 19-2: 19.7.
PIC18FXX8 19.8 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2, as necessary. There are two mechanisms used for synchronization. 19.
PIC18FXX8 FIGURE 19-9: Sync SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Segment Phase Segment 1 TQ Phase Segment 2 ≤ SJW Sample Point Actual Bit Length Nominal Bit Length 19.9 Programming Time Segments Some requirements for programming of the time segments: • Prop Seg + Phase Seg 1 ≥ Phase Seg 2 • Phase Seg 2 ≥ Sync Jump Width For example, assume that a 125 kHz CAN baud rate is desired using 20 MHz for FOSC.
PIC18FXX8 19.12 Error Detection 19.12.6 The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states “error-active”, “error-passive” or “bus-off” according to the value of the internal error counters.
PIC18FXX8 FIGURE 19-10: ERROR MODES STATE DIAGRAM Reset ErrorActive RXERRCNT < 127 or TXERRCNT < 127 128 occurrences of 11 consecutive “recessive” bits RXERRCNT > 127 or TXERRCNT > 127 ErrorPassive TXERRCNT > 255 BusOff 19.13 CAN Interrupts 19.13.1 The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The CANINTF register contains interrupt flags. The CANINTE register contains the enables for the 8 main interrupts.
PIC18FXX8 TABLE 19-3: VALUES FOR ICODE<2:0> ICOD <2:0> Interrupt Boolean Expression 000 None ERR•WAK•TX0•TX1•TX2•RX0• RX1 001 Error ERR 010 TXB2 ERR•TX0•TX1•TX2 011 TXB1 ERR•TX0•TX1 100 TXB0 ERR•TX0 101 RXB1 ERR•TX0•TX1•TX2•RX0•RX1 110 RXB0 ERR•TX0•TX1•TX2•RX0 111 Wake on Interrupt ERR•TX0•TX1•TX2•RX0•RX1• WAK Key: ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE TX2 = TXB2IF * TXB2IE 19.13.
PIC18FXX8 NOTES: DS41159E-page 240 © 2006 Microchip Technology Inc.
PIC18FXX8 20.0 COMPATIBLE 10-BIT ANALOGTO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has five inputs for the PIC18F2X8 devices and eight for the PIC18F4X8 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the PICmicro® mid-range A/D module. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. REGISTER 20-1: The A/D module has four registers.
PIC18FXX8 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
PIC18FXX8 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS) or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF- pin. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.
PIC18FXX8 The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 6. 7. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 “A/D Acquisition Requirements”.
PIC18FXX8 To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 20-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: • • • • • • CHOLD Rs Conversion Error VDD Temperature VHOLD EQUATION 20-1: TACQ 120 pF 2.
PIC18FXX8 20.2 Selecting the A/D Conversion Clock 20.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: • • • • • • • Configuring Analog Port Pins The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input).
PIC18FXX8 20.4 20.4.1 A/D Conversions Figure 20-4 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will not be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
PIC18FXX8 20.5 Use of the ECCP Trigger acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the “special event trigger” of the ECCP module.
PIC18FXX8 21.0 Note: COMPARATOR MODULE The analog comparators are available on the PIC18F448 PIC18F458. only and The CMCON register, shown in Register 21-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 21-1. The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RD0 through RD3 pins. The on-chip voltage reference (Section 22.
PIC18FXX8 21.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 21-1 shows the eight possible modes. The TRISD register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 21-1: A VIN- RD0/PSP0 A VIN+ A VIN- RD3/PSP3 RD2/PSP2 A Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur.
PIC18FXX8 21.2 21.3.2 Comparator Operation A single comparator is shown in Figure 21-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18FXX8 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RE1 or RE2 pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18FXX8 21.7 Comparator Operation During Sleep 21.8 A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Comparator Reset mode, CM<2:0> = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at Reset time. The comparators will be powered down during the Reset interval.
PIC18FXX8 TABLE 21-1: Name CMCON REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 INTCON TMR0IF INT0IF RBIF 0000 000x 0000 000u GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE PIR2 — CMIF(1) — EEIF BCLIF LVDIF PIE2 — CMIE(1) — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1
PIC18FXX8 22.0 Note: COMPARATOR VOLTAGE REFERENCE MODULE 22.1 The comparator voltage reference is only available on the PIC18F448 and PIC18F458. This module is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference, as shown in Register 22-1.
PIC18FXX8 FIGURE 22-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 1 CVREN 16 Stages CVRSS = 0 8R R R R R CVRR 8R CVRSS = 1 CVRSS = 0 RA0/AN0/CVREF or CVREF of Comparator 22.2 16-to-1 Analog MUX Voltage Reference Accuracy/Error 22.4 RA2/AN2/VREFCVR3 (From CVRCON<3:0>) CVR0 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module.
PIC18FXX8 FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RA0/AN0 • + – • CVREF Output Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration CVRCON<3:0> and CVRCON<5>.
PIC18FXX8 NOTES: DS41159E-page 258 © 2006 Microchip Technology Inc.
PIC18FXX8 23.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified.
PIC18FXX8 FIGURE 23-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVDL3:LVDL0 LVDCON Register 16-to-1 MUX VDD Internally Generated Reference Voltage, 1.2V Typical LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin LVDIN to one input of the comparator (Figure 23-3).
PIC18FXX8 23.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry.
PIC18FXX8 23.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC18FXX8 23.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36.
PIC18FXX8 NOTES: DS41159E-page 264 © 2006 Microchip Technology Inc.
PIC18FXX8 24.0 SPECIAL FEATURES OF THE CPU Sleep mode is designed to offer a very Low-Current Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits is used to select various options.
PIC18FXX8 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 — — OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FOSC2:FOSC
PIC18FXX8 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — bit 7 bit 7-4 bit 3-1 U-0 — U-0 — R/P-1 WDTPS2 R/P-1 WDTPS0 R/P-1 WDTEN bit 0 The Watchdog Timer postscale select bits configuration used in the PIC18FXXX devices has changed from the configuration used in the PIC18CXXX devices.
PIC18FXX8 REGISTER 24-5: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code-protected 0 = Block 2 (004000-005FFFh) code-protected bit 1 CP1: Code Protection bit
PIC18FXX8 REGISTER 24-7: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-007FFFh) write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write-protected 0 = Block 2 (004000-005FFFh) write-protected bit 1 WRT1: Write
PIC18FXX8 REGISTER 24-9: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFF
PIC18FXX8 REGISTER 24-11: DEVID1: DEVICE ID REGISTER 1 FOR PIC18FXX8 DEVICES (BYTE ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number. 000 = PIC18F248 001 = PIC18F448 010 = PIC18F258 011 = PIC18F458 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
PIC18FXX8 24.2 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. The WDT time-out period values may be found in Section 27.0 “Electrical Characteristics” under parameter #31.
PIC18FXX8 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of device programming by the value written to the CONFIG2H Configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 WDTPS2:WDTPS0 8-to-1 MUX WDTEN Configuration bit SWDTEN bit WDT Time-out Note: TABLE 24-2: Name CONFIG2H RCON WDTCON WDTPS2:WDTPS0 are bits in register CONFIG2H.
PIC18FXX8 24.3 Power-Down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (RCON<2>) is cleared, the TO bit (RCON<3>) is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance).
PIC18FXX8 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 24-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC Instruction Fetched Inst(PC) = Sleep Instruction Inst(PC – 1) Executed Note 1: 2: 3: 4: PC + 2 Inst(PC + 2) Sleep PC + 4 PC + 4 PC + 4 Inst(PC + 4) Inst(PC + 2) Dummy Cycle 0008h 000Ah Inst(0008h) Inst(000Ah) Dumm
PIC18FXX8 24.4 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 512 bytes.
PIC18FXX8 24.4.1 PROGRAM MEMORY CODE PROTECTION Note: The user memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In user mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is ‘0’.
PIC18FXX8 FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0, EBTR0 = 10 001FFFh 002000h PC = 002FFE TBLRD * WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18FXX8 24.4.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 24.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers.
PIC18FXX8 NOTES: DS41159E-page 280 © 2006 Microchip Technology Inc.
PIC18FXX8 25.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations.
PIC18FXX8 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location.
PIC18FXX8 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-b
PIC18FXX8 TABLE 25-2: PIC18FXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d
PIC18FXX8 TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s NOP NOP POP PUSH RCALL RESET RETFIE — — — — n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine1st word 2nd word Clear Wat
PIC18FXX8 TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from liter
PIC18FXX8 25.2 Instruction Set ADDLW ADD Literal to W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: ADDWF k 1111 kkkk 1 Cycles: 1 Syntax: [ label ] ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z kkkk The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18FXX8 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] (W) + (f) + (C) → dest Operation: Status Affected: Encoding: 0010 Description: 00da ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected.
PIC18FXX8 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 ffff ffff The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden (default).
PIC18FXX8 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: 1001 f,b[,a] ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).
PIC18FXX8 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch.
PIC18FXX8 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch.
PIC18FXX8 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18FXX8 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff Encoding: 1010 If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18FXX8 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Encoding: bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18FXX8 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (Status) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18FXX8 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1→Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18FXX8 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] CPFSEQ Compare f with W, Skip if f = W Syntax: [ label ] CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None ( f ) → dest Operation: Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18FXX8 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: f [,a] 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents
PIC18FXX8 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0> 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; else (W<7:4>) → W<7:4> Status Affected: 0000 0000 Description: 0000 0000 Words: Cycles: Words: 1 Cy
PIC18FXX8 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18FXX8 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z GOTO k Operands: 0 ≤ k ≤ 1048575 Operation: k → PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18FXX8 INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ f [,d [,a]] 11da ffff ffff Encoding: INFSNZ 0100 f [,d [,a]] 10da ffff ffff Description: The contents of register ‘f’ are inc
PIC18FXX8 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18FXX8 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18FXX8 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: (fs) → fd k → BSR Operation: Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (destin.) MOVFF fs,fd Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18FXX8 MOVLW Move Literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) → f Status Affected: None MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k→W Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18FXX8 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18FXX8 NEGF Negate f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] NEGF Operation: (f)+1→f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: f [,a] 1 Cycles: 1 110a ffff Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff 0000 xxxx Description: No operation.
PIC18FXX8 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 POP 0000 0000 0110 Encoding: PUSH 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18FXX8 RCALL Relative Call Syntax: [ label ] RCALL n RESET Reset Syntax: [ label ] RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18FXX8 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged.
PIC18FXX8 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z RETURN [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subrout
PIC18FXX8 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18FXX8 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 Description: RRNCF f [,d [,a]] 00da Operation: FFh → f Status Affected: None Encoding: ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18FXX8 SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z SLEEP Operands: None Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18FXX8 SUBLW Subtract W from Literal SUBWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: SUBLW k 0000 Description: 1000 kkkk kkkk Subtract W from f SUBWF f [,d [,a]] W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18FXX8 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: SUBWFB 10da f [,d [,a]] ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18FXX8 TBLRD Table Read Syntax: [ label ] Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT TBLRD ( *; *+; *-; +*) Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program
PIC18FXX8 TBLWT Table Write Syntax: [ label ] TBLWT Table Write (Continued) TBLWT ( *; *+; *-; +*) Words: 1 Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; (TABLAT) → Holding Register; Q Cycle Activity: Description: 0000 0000 0000 Q3 Q4 No operation No operation No operation Exam
PIC18FXX8 TSTFSZ Test f, Skip if 0 Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: skip if f = 0 Status Affected: None Encoding: TSTFSZ f [,a] Exclusive OR Literal with W Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Status Affected: N, Z Encoding: 0110 Description: XORLW 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18FXX8 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 XORWF 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18FXX8 26.
PIC18FXX8 26.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.
PIC18FXX8 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18FXX8 26.14 PICSTART Plus Development Programmer 26.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins.
PIC18FXX8 26.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
PIC18FXX8 NOTES: DS41159E-page 328 © 2006 Microchip Technology Inc.
PIC18FXX8 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.
PIC18FXX8 FIGURE 27-1: PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18FXX8 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 27-2: PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18FXX8 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency DS41159E-page 330 © 2006 Microchip Technology Inc.
PIC18FXX8 FIGURE 27-3: PIC18LFXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LFXX8 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V = 40 MHz, if VDDAPPMIN > 4.2V Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. © 2006 Microchip Technology Inc.
PIC18FXX8 27.1 DC Characteristics PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX8 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. VDD D001 D001 Characteristic/ Device Min Typ Max Units PIC18LFXX8 2.0 — 5.5 V PIC18FXX8 Conditions Supply Voltage 4.2 — 5.
PIC18FXX8 27.1 DC Characteristics (Continued) PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX8 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. IDD Characteristic/ Device Min Typ Max Units Conditions — — — .7 .7 1.7 2 2 4 mA mA mA — — — 1 1 2.5 2.5 2.
PIC18FXX8 27.1 DC Characteristics (Continued) PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX8 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. IDD D010C Characteristic/ Device Min Typ Max Units — 21 28 mA — 21 30 mA — — 1.
PIC18FXX8 27.1 DC Characteristics (Continued) PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX8 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No.
PIC18FXX8 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic/ Device Min Max Units Conditions with TTL buffer VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V with Schmitt Trigger buffer RC3 and RC4 VSS VSS 0.2 VDD 0.
PIC18FXX8 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic/ Device D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions — 0.6 V IOL = 8.5 mA, VDD = 4.2V, -40°C to +85°C — 0.6 V IOL = 7.0 mA, VDD = 4.
PIC18FXX8 FIGURE 27-4: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) 37 LVDIF TABLE 27-1: LOW-VOLTAGE DETECT CHARACTERISTICS Low-Voltage Detect Characteristics Param Symbol No. D420 VLVD DS41159E-page 338 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Characteristic LVD Voltage Min Typ Max Units Conditions LVV = 0001 1.96 2.06 2.
PIC18FXX8 TABLE 27-2: DC CHARACTERISTICS: EEPROM AND ENHANCED FLASH DC Characteristics Param No. Sym Standard Operating Conditions Characteristic Min Typ† Max Units 9.00 — 13.
PIC18FXX8 TABLE 27-3: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Section 27.1 “DC Characteristics”, -40°C < TA < +125°C Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.
PIC18FXX8 27.3 27.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS 3. TCC:ST 4.
PIC18FXX8 27.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-5 specifies the load conditions for the timing specifications.
PIC18FXX8 27.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: Param Symbol No. 1A 1 FOSC TOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Max External CLKI Frequency(1) Oscillator Frequency(1) DC 40 MHz EC, ECIO oscillator, -40°C to +85°C DC 25 MHz EC, ECIO oscillator, +85°C to +125°C DC 4 MHz RC oscillator 0.
PIC18FXX8 TABLE 27-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Sym Characteristic Min Typ† Max Units Conditions HS mode only HS mode only — — FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency 4 16 — — 10 40 MHz MHz — trc PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % — † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC18FXX8 FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 27-5 for load conditions. FIGURE 27-9: BROWN-OUT RESET AND LOW-VOLTAGE DETECT TIMING BVDD (for 35) VLVD (for 37) VDD 35, 37 VBGAP = 1.
PIC18FXX8 FIGURE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-5 for load conditions. TABLE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No.
PIC18FXX8 FIGURE 27-11: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND ECCP1) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 54 53 Note: Refer to Figure 27-5 for load conditions. TABLE 27-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND ECCP1) Param Symbol No. 50 TccL Characteristic CCPx Input Low Time No prescaler With prescaler 51 TccH PIC18FXX8 PIC18LFXX8 52 TccP CCPx Input Period 53 TccR CCPx Output Fall Time 54 TccF CCPx Output Fall Time © 2006 Microchip Technology Inc.
PIC18FXX8 FIGURE 27-12: PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 27-5 for load conditions. TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458) Param No. 62 Symbol TdtV2wrH Characteristic Min Max Units Conditions Data-In Valid before WR ↑ or CS ↑ (setup time) 20 25 — — ns ns Extended Temp.
PIC18FXX8 FIGURE 27-13: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-5 for load conditions. TABLE 27-13: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18FXX8 FIGURE 27-14: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO Bit 6 - - - - - -1 LSb Bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-14: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param No. 71 Symbol TscH 71A 72 TscL 72A Characteristic Min Max Units SCK Input High Time (Slave mode) Continuous 1.
PIC18FXX8 FIGURE 27-15: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO MSb Bit 6 - - - - - -1 LSb 77 75, 76 SDI MSb In 73 Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0) Param No.
PIC18FXX8 FIGURE 27-16: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1) 82 SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO LSb Bit 6 - - - - - -1 77 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-16: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18FXX8 FIGURE 27-17: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param No.
PIC18FXX8 TABLE 27-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param No. 100 Symbol THIGH Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — μs PIC18FXX8 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXX8 must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — μs PIC18FXX8 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXX8 must operate at a minimum of 10 MHz 1.5 TCY — ns — 1000 ns 20 + 0.
PIC18FXX8 MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-19: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol No.
PIC18FXX8 TABLE 27-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18FXX8 FIGURE 27-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 27-5 for load conditions. TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18FXX8 TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED) PIC18LFXX8 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units bit Conditions VREF = VDD ≥ 3.0V A01 NR Resolution — — 10 A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD ≥ 3.0V A05 EFS Full Scale Error — — <±1 LSb VREF = VDD ≥ 3.0V A06 EOFF Offset Error — — <±1.5 LSb VREF = VDD ≥ 3.
PIC18FXX8 FIGURE 27-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
PIC18FXX8 NOTES: DS41159E-page 360 © 2006 Microchip Technology Inc.
PIC18FXX8 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18FXX8 FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 26 24 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 22 5.0V 20 4.5V 18 16 IDD (mA) 4.2V 14 12 10 8 6 4 2 0 4 5 6 7 8 9 10 FOSC (MHz) FIGURE 28-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 28 5.5V 26 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 24 22 5.0V 4.5V 20 18 4.
PIC18FXX8 FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.0 5.5V 5.0V 2.5 4.5V 4.0V IDD (mA) 2.0 3.5V 3.0V 1.5 2.5V 1.0 2.0V 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 28-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 4.0 3.5 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 5.0V 3.
PIC18FXX8 FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 700 5.5V 600 5.0V 4.5V 500 4.0V 400 IDD (μA) 3.5V 3.0V 300 2.5V 2.0V 200 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 100 0 20 30 40 50 60 70 80 90 100 80 90 100 FOSC (kHz) FIGURE 28-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 900 800 5.5V 700 5.0V 600 IDD (μA) 4.5V 500 4.0V 3.5V 400 3.0V 2.5V 300 2.
PIC18FXX8 FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 24 5.5V 22 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 20 5.0V IDD (mA) 18 4.5V 16 4.2V 14 4.0V 12 10 3.5V 8 6 3.0V 4 2.5V 2 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 28-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 28 26 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 24 5.
PIC18FXX8 FIGURE 28-11: TYPICAL AND MAXIMUM IDD vs. VDD (TIMER1 AS MAIN OSCILLATOR 32.768 kHz, C1 AND C2 = 47 pF) 1200 1000 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-10°C to +70°C) Minimum: mean – 3σ (-10°C to +70°C) IDD (μA) 800 600 400 Max (70°C) 200 Typ (25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C) 4,500 Operation above 4 MHz is not recommended. 4,000 3.
PIC18FXX8 FIGURE 28-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C) 2,000 1,800 1,600 3.3kΩ 1,400 Freq (kHz) 1,200 5.1kΩ 1,000 800 600 10kΩ 400 200 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 28-14: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C) 800 700 3.3kΩ 600 Freq (MHz) 500 5.1kΩ 400 300 10kΩ 200 100 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 VDD (V) © 2006 Microchip Technology Inc.
PIC18FXX8 FIGURE 28-15: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (-40°C to +125°C) 10 (μ A) Max (+85°C) I 1 Typ (+25°C) 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V D D (V ) FIGURE 28-16: ΔIBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00-2.
PIC18FXX8 FIGURE 28-17: TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF) 14 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-10°C to +70°C) Minimum: mean – 3σ (-10°C to +70°C) 12 Max Max(+70°C) (70C) 10 IPD (uA) (μA) 8 Typ Typ(+25°C) (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-18: TYPICAL AND MAXIMUM ΔIWDT vs.
PIC18FXX8 FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C) 50 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 45 40 Max Max (+125°C) (125C) 35 WDT Period (ms) Max MAX (+85°C) (85C) 30 25 Typ (+25°C) (25C) 20 15 Min Min (-40°C) (-40C) 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-20: ΔILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.
PIC18FXX8 FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 Max Max 4.0 Typ Typ(+25°C) (25C) VOH (V) 3.5 3.0 Min Min 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.0 2.5 2.0 VOH (V) Max Max 1.5 Typ Typ(+25°C) (25C) 1.0 Min Min 0.5 0.0 0 5 10 15 20 25 IOH (-mA) © 2006 Microchip Technology Inc.
PIC18FXX8 FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.8 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.4 VOL (V) 1.2 1.0 Max Max 0.8 0.6 0.4 Typ (+25°C) Typ (25C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 2.
PIC18FXX8 FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.5 VIH Max 3.0 2.5 VIN (V) VIH Min 2.0 VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.
PIC18FXX8 MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40°C TO +125°C) FIGURE 28-27: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.0 2.5 2.0 VIN (V) VVILILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-28: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.
PIC18FXX8 FIGURE 28-29: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) © 2006 Microchip Technology Inc.
PIC18FXX8 NOTES: DS41159E-page 376 © 2006 Microchip Technology Inc.
PIC18FXX8 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP Example PIC18F258-I/SP e3 0610017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18FXX8 29.1 Package Marking Information (Continued) 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS41159E-page 378 Example PIC18F458 -I/L e3 0610017 Example PIC18F448 -I/PT e3 0610017 © 2006 Microchip Technology Inc.
PIC18FXX8 29.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN 28 NOM MAX 28 .100 2.54 Top to Seating Plane A .140 .
PIC18FXX8 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.
PIC18FXX8 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC18FXX8 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 35° A B1 B c β E2 Units Dimension Limits n p A1 p D2 INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .
PIC18FXX8 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) n1 A A2 A1 L F φ MIN .039 .037 .002 .018 INCHES NOM 44 .
PIC18FXX8 NOTES: DS41159E-page 384 © 2006 Microchip Technology Inc.
PIC18FXX8 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision A (June 2001) Original data sheet for the PIC18FXX8 family. Revision B (May 2002) Updated information on CAN module, device memory and register maps, I/O ports and Enhanced CCP. Revision C (January 2003) This revision includes the DC and AC Characteristics Graphs and Tables (see Section 28.
PIC18FXX8 APPENDIX C: DEVICE MIGRATIONS This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable APPENDIX D: MIGRATING FROM OTHER PICmicro® DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC18FXX8 family of devices. D.
PIC18FXX8 INDEX A A/D .................................................................................... 241 A/D Converter Flag (ADIF Bit) .................................. 243 A/D Converter Interrupt, Configuring ........................ 244 Acquisition Requirements ......................................... 244 Acquisition Time........................................................ 245 ADCON0 Register..................................................... 241 ADCON1 Register..............................
PIC18FXX8 BSF ................................................................................... 293 BTFSC .............................................................................. 294 BTFSS............................................................................... 294 BTG................................................................................... 295 BZ...................................................................................... 296 C C Compilers MPLAB C17 .......................
PIC18FXX8 Code Examples 16 x 16 Signed Multiply Routine ................................. 76 16 x 16 Unsigned Multiply Routine ............................. 76 8 x 8 Signed Multiply Routine ..................................... 75 8 x 8 Unsigned Multiply Routine ................................. 75 Changing Between Capture Prescalers.................... 125 Data EEPROM Read .................................................. 61 Data EEPROM Refresh Routine.................................
PIC18FXX8 Enhanced CCP Auto-Shutdown........................................ 142 Enhanced PWM Mode. See PWM (ECCP Module). Errata .................................................................................... 5 Error Recognition Mode (CAN Module) ............................ 226 Evaluation and Programming Tools .................................. 327 External Clock Input ............................................................ 19 F Firmware Instructions.............................................
PIC18FXX8 NEGF ........................................................................ 309 NOP .......................................................................... 309 POP .......................................................................... 310 PUSH ........................................................................ 310 RCALL ...................................................................... 311 RESET ...................................................................... 311 RETFIE ...
PIC18FXX8 O Opcode Field Descriptions ................................................ 282 Oscillator Effects of Sleep Mode ................................................. 23 Power-up Delays......................................................... 23 Switching Feature ....................................................... 20 System Clock Switch Bit ............................................. 20 Transitions .................................................................. 21 Oscillator Configurations .
PIC18FXX8 Prescaler, Timer2.............................................................. 128 PRO MATE II Universal Device Programmer .............................................................. 325 Program Counter PCL Register............................................................... 40 PCLATH Register ....................................................... 40 PCLATU Register ....................................................... 40 Program Memory ...................................................
PIC18FXX8 RXBnSIDL (Receive Buffer n Standard Identifier, Low Byte)........................... 212 RXERRCNT (Receive Error Count) .......................... 214 RXFnEIDH (Receive Acceptance Filter n Extended Identifier, High Byte) ......................... 216 RXFnEIDL (Receive Acceptance Filter n Extended Identifier, Low Byte) .......................... 216 RXFnSIDH (Receive Acceptance Filter n Standard Identifier Filter, High Byte).................
PIC18FXX8 Timer1 ............................................................................... 113 16-bit Read/Write Mode ............................................ 115 Associated Registers ................................................ 116 Operation .................................................................. 114 Oscillator ........................................................... 113, 115 Overflow Interrupt ............................................. 113, 115 Special Event Trigger (CCP)...
PIC18FXX8 Transition from OSC1 to Timer1 Oscillator................................................. 21 USART Asynchronous Reception ............................. 192 USART Asynchronous Transmission........................ 190 USART Asynchronous Transmission (Back to Back)................................................... 190 USART Synchronous Receive (Master/Slave)................................................... 357 USART Synchronous Reception (Master Mode, SREN).......................................
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PIC18FXX8 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18FXX8 PIC18FXX8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC18F248/258(1), PIC18F448/458(1), (2) PIC18F248/258T(2), PIC18F448/458T ; VDD range 4.2V to 5.5V PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2), PIC18LF448/458T(2); VDD range 2.0V to 5.
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