Information

PIC18F2458/2553/4458/4553
DS80336D-page 2 © 2008 Microchip Technology Inc.
2. Module: MSSP
With MSSP in SPI Master mode, FOSC/64 or
Timer2/2 clock rate and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• A non-zero dead-band delay is specified
(PDC6:PDC0 > 0)
• The duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1)
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Electrical Characteristics (BOR)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the device data sheet (parameter D005).
The BOR threshold has been observed to increase
with high device operating frequencies, some table
read operations and heavy loading on the USB
voltage regulator. When all of these conditions are
present, BOR has been observed with V
DD
20 percent higher than the VBOR value specified
for a given <BORV1:BORV0> setting.
The BOR threshold may decrease under other
conditions, such as during Sleep, where it may not
occur until V
DD is 120 mV below the specified
minimums.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: MSSP (SPI Slave)
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM3:SSPM0 = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and the process variations between the
microcontrollers.
Experimentation and thorough testing are
encouraged.
Date Codes that pertain to this issue:
All engineering and production devices.