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PIC18F2423/2523/4423/4523

The PIC18F2423/2523/4423/4523 Rev. B2 parts you

have received conform functionally to the Device Data

Sheet (DS39755B), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F2423/2523/4423/4523 will be

reported in a separate Data Sheet errata. Please check

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2423/2523/4423/4523 devices with these

Device/Revision IDs:

1. Module: MSSP

In SPI Slave mode with slave select enabled

(SSPM<3:0> = 0100), the minimum time between

the falling edge of the SS pin and first SCK edge

is greater than specified in parameter 70 in

Table 26-14 and Table 26-16. The updated

specification is shown in bold in Table 1.

The minimum time between SS

pin low and an

SSPBUF write is also 3 T

CY. If the falling edge of

the SS

pin occurs greater than 3 TCY before the

first SCK edge, or loading SSPBUF, the peripheral

will function correctly. Also, if SSPBUF is written

prior to the SS

pin going low, the peripheral will

function correctly.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

TABLE 1: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)

Part Number Device ID Revision ID

PIC18F2423 0001 0001 010 10101

PIC18F2523 0001 0001 000 10101

PIC18F4423 0001 0000 110 10101

PIC18F4523 0001 0000 100 10101

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

Param

No.

Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

↓ to SCK ↓ or SCK ↑ Input 3TCY —ns

PIC18F2423/2523/4423/4523 Rev. B2 Silicon Errata

Summary of content (8 pages)

PAGE 1
PIC18F2423/2523/4423/4523 PIC18F2423/2523/4423/4523 Rev. B2 Silicon Errata The PIC18F2423/2523/4423/4523 Rev. B2 parts you have received conform functionally to the Device Data Sheet (DS39755B), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2423/2523/4423/4523 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues.
PAGE 2
PIC18F2423/2523/4423/4523 2. Module: MSSP 4. Module: ECCP (PWM Mode) With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate, and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set and before writing SSPBUF. If the delay is insufficiently short, a write collision may occur, as indicated by the WCOL bit being set.
PAGE 3
PIC18F2423/2523/4423/4523 5. Module: Enhanced Universal Synchronous Receiver Transmitter (EUSART) Register 18-3, on page 208, will be changed as shown. Work around One bit has been added to the BAUDCON register and one bit has been renamed. The added bit is RXDTP and is in the location, BAUDCON<5>. The renamed bit is the TXCKP bit (BAUDCON<4>), which had been named SCKP. None required. Date Codes that pertain to this issue: All engineering and production devices.
PAGE 4
PIC18F2423/2523/4423/4523 6. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1). FIGURE 1: SCK PULSE VARIATION USING TIMER2/2 Write SSPBUF bit 0 = 1 bit 1 = 0 bit 2 = 1 . . . . 7.
PAGE 5
PIC18F2423/2523/4423/4523 REVISION HISTORY Rev A Document (08/2006) First revision of this document. Silicon issues 1-2 (MSSP). Rev B Document (10/2006) Added silicon issue 3 (Timer1 and Timer3). Rev C Document (11/2006) Updated silicon issue 3 (Timer1 and Timer3) and added silicon issue 4 (ECCP – PWM Mode). Rev D Document (5/2007) Added silicon issue 5 (Enhanced Universal Synchronous Receiver Transmitter – EUSART) and 6 (MSSP – SPI Mode). Rev E Document (6/2007) Added silicon issue 7 (12-Bit Converter).
PAGE 7
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 8
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