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PIC18F2515/2610/4515/4610 FAMILY
DS80416A-page 4 © 2008 Microchip Technology Inc.
5. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: Enhanced Universal
Synchronous Receiver
Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTA<7> = 0)
• The EUSART is re-enabled (RCSTA<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 TCY delay after re-enabling the EUSART.
1. Disable Receive Interrupts (RCIE bit,
PIE1<5> = 0).
2. Disable the EUSART (RCSTA<7> = 0).
3. Re-enable the EUSART (RCSTA<7> = 1).
4. Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first TCY delay.)
5. Execute a NOP instruction.
(This is the second T
CY delay.)
Date Codes that pertain to this issue:
All engineering and production devices.