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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 40 MHz I/O number 25

PIC18F2515/2610/4515/4610

The PIC18F2515/2610/4515/4610 Rev. B4 parts you

have received conform functionally to the Device Data

Sheet (DS39636C), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F2515/2610/4515/4610 will be

reported in a separate Data Sheet errata. Please check

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2515/2610/4515/4610 devices with these

Device/Revision IDs:

1. Module: MSSP

In SPI Slave mode with Slave Select enabled

(SSPM3:0 = 0b0100), the minimum time between

the falling edge of SS pin and first SCK edge is

greater than specified in parameter 70 in Table

25-16. The updated specification is shown in bold in

Tabl e 1.

The minimum time between SS

pin low and an

SSPBUF write is also 3 T

CY. If the falling edge of

pin occurs greater than 3Tcy before the first

SCK edge or loading SSPBUF, the peripheral will

function correctly. Also, if SSPBUF is written prior

to SS

pin going low, the peripheral will function

correctly.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

TABLE 1: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)

Part Number Device ID Revision ID

PIC18F2515 0000 1100 111 0 0110

PIC18F2610 0000 1100 101 0 0110

PIC18F4515 0000 1100 011 0 0110

PIC18F4610 0000 1100 001 0 0110

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

Param

No.

Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

↓ to SCK↓ or SCK↑ Input 3 TCY —ns

PIC18F2515/2610/4515/4610 Rev. B4 Silicon Errata

Summary of content (6 pages)

PAGE 1
PIC18F2515/2610/4515/4610 PIC18F2515/2610/4515/4610 Rev. B4 Silicon Errata The PIC18F2515/2610/4515/4610 Rev. B4 parts you have received conform functionally to the Device Data Sheet (DS39636C), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2515/2610/4515/4610 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues.
PAGE 2
PIC18F2515/2610/4515/4610 2. Module: MSSP With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set and before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set. Work around 4.
PAGE 3
PIC18F2515/2610/4515/4610 REGISTER 17-3: R/W-0 BAUDCON: BAUD RATE CONTROL REGISTER R-1 ABDOVF RCIDL R/W-0 RXDTP R/W-0 TXCKP R/W-0 U-0 R/W-0 R/W-0 BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No B
PAGE 4
PIC18F2515/2610/4515/4610 5. Module: 10-Bit Analog-to-Digital (A/D) Converter When the A/D clock source is selected as 2 TOSC or RC (when ADCS2:ADCS0 = 000 or x11), in extremely rare cases, the EIL (Integral Linearity Error) and EDL (Differential Linearity Error) may exceed the data sheet specification at codes 511 and 512 only. Work around Select a different A/D clock source (4 TOSC, 8 TOSC, 16 TOSC, 32 TOSC, 64 TOSC) and avoid selecting the 2 TOSC or RC modes.
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
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