Datasheet

PIC18F2X1X/4X1X
DS39636D-page 350 © 2009 Microchip Technology Inc.
FIGURE 25-23: A/D CONVERSION TIMING
TABLE 25-25: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period PIC18FXXXX 0.7 25.0
(1)
μsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0
(1)
μsVDD = 2.0V;
T
OSC based, VREF full range
PIC18FXXXX TBD 1 μs A/D RC mode
PIC18LFXXXX TBD 3 μsV
DD = 2.0V; A/D RC mode
131 TCNV Conversion Time
(not including acquisition time) (Note 2)
11 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4
TBD
—
—
μs
μs
-40°C to +85°C
0°C ≤ to ≤ +85°C
135 T
SWC Switching Time from Convert → Sample — (Note 4)
TBD TDIS Discharge Time 0.2 — μs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following T
CY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.