Datasheet

© 2009 Microchip Technology Inc. DS39636D-page 135
PIC18F2X1X/4X1X
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN
SBOREN
(2)
— RI TO PD POR BOR 50
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2
OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54
TRISB PORTB Data Direction Control Register 54
TRISC PORTC Data Direction Control Register 54
TMR1L Timer1 Register Low Byte 52
TMR1H Timer1 Register High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 52
TMR3H Timer3 Register High Byte 53
TMR3L Timer3 Register Low Byte 53
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON
P1M1
(1)
P1M0
(1)
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
CCPR2L Capture/Compare/PWM Register 2 Low Byte 53
CCPR2H Capture/Compare/PWM Register 2 High Byte 53
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.
2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is
disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.