Datasheet

© 2009 Microchip Technology Inc. DS39636D-page 113
PIC18F2X1X/4X1X
FIGURE 9-3: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 9-4: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54
LATD PORTD Data Latch Register (Read and Write to Data Latch) 54
TRISD PORTD Data Direction Control Register 54
PORTE
— — — — RE3 RE2 RE1 RE0 54
LATE
— — — — — LATE Data Output bits 54
TRISE IBF OBF IBOV PSPMODE
— TRISE2 TRISE1 TRISE0 54
INTCON GIE/GIEH PEIE/GIEL
TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>