Information

 2009-2013 Microchip Technology Inc. DS80000435K-page 7
PIC18F46J11
11. Module: Charge Time Measurement Unit
(CTMU)
On the F devices, the CTMU current source will
stop sourcing current if the applied V
DD voltage
falls below the LVDSTAT (WDTCON<6>) threshold
(2.45V nominal). When VDD is above the LVDSTAT
threshold, the CTMU will function normally.
This issue does not apply to the LF devices. The
current source will continue functioning normally
at all rated voltages for these devices.
Work around
None.
Affected Silicon Revisions
12. Module: Analog-to-Digital Converter (A/D)
At the beginning of sample acquisition, one or
more small, pull-up pulses (approximately 25 ns
long) may output to the currently selected ANx
analog channel. These pulses can lead to a
positive offset error when the analog signal
voltage is near V
SS and the external analog
signal driver is unable to dissipate the added
pull-up voltage before the A/D conversion
occurs.
Work around
Do one or more of the following:
• Use the “0 T
AD” A/D Acquisition Time setting
to start the next sample acquisition period
immediately following A/D conversion
completion.
This allows the external analog signal driver
more time to dissipate the pull-up pulses that
occur when the sample acquisition is started.
• Use a longer A/D Acquisition Time setting to
provide time for the external analog signal
driver to dissipate the pull-up pulse voltage.
• Use low-impedance, active analog signal
drivers to reduce the time needed to dissipate
the pull-up pulse voltage.
• Experiment with external filter capacitor values
to avoid allowing the pull-up voltage offset to
affect the final voltage that gets converted.
Small filter capacitor values (or none at all) will
allow time for the external analog signal driver
to dissipate the pull-up voltage quickly.
Alternately, large filter capacitor values will
prevent the short pull-up pulses from increasing
the final voltage enough to cause A/D
conversion error.
Affected Silicon Revisions
A2 A4
X
A2 A4
X
X