Information

PIC18F46J11
DS80000435K-page 6  2009-2013 Microchip Technology Inc.
7. Module: DC Characteristics (Supply
Voltage)
The minimum operating voltage (VDD) parameter
(D001) for the F devices is 2.25V. For the LF
devices (such as PIC18LF46J11), the minimum
rated V
DD operating voltage is 2.0V.
Work around
None.
Affected Silicon Revisions
8. Module: Special Features (T1DIG)
The T1DIG Configuration bit (CONFIG2L<3>)
function is not implemented. Effectively, T1DIG
is ‘0’ regardless of the value programmed into
the bit.
Work around
None.
Affected Silicon Revisions
9. Module: Master Synchronous Serial Port
(MSSP) – Port 1
When MSSP1 is used in I
2
C mode, the correct
data and clock signals are present on the RC3
and RC4 pins. The RB4 and RB5 pins, however,
may have extraneous pulses that prevent them
from being used normally.
Work around
The RC3 and RC4 pins retain the correct clock
and data signals, so the device should be
connected to the I
2
C bus through these pins. If
TRISB<5> remains cleared, RB5 can be used
as a general purpose output pin under normal
firmware control.
This issue applies only to MSSP1 when used in
the I
2
C mode.
No work around is necessary if MSSP1 is used
in an SPI mode or if MSSP2 is used.
Affected Silicon Revisions
10. Module: 10-Bit Analog-to-Digital
Converter (A/D) – Band Gap
Reference
At high VDD voltages (for example, > 2.5V),
performing an A/D conversion on Channel 15
(the VBG absolute reference) can temporarily
disturb the reference voltage supplied to the
HLVD module and comparator module (only
when configured to use the V
IRV).
At lower V
DD voltages, the disturbance will be
less or non-existent.
Work around
If precise HLVD or comparator VIRV thresholds
are required at high V
DD voltages, avoid
performing A/D conversions on Channel 15
while simultaneously using the HLVD or
comparator, V
IRV. If an A/D conversion is
performed on Channel 15, a settling time of
approximately 100 s is needed before the
reference voltage fully returns to the original
value.
Affected Silicon Revisions
A2 A4
X
A2 A4
X
X
A2
A4
X
A2 A4
X
X