Information

 2009-2013 Microchip Technology Inc. DS80000435K-page 5

PIC18F46J11

6. Module: Low-Power Modes (Deep Sleep)

Entering Deep Sleep mode takes approximately

CY, following the SLEEP instruction. Wake-up

events that occur during this Deep Sleep entry

period may not generate a wake-up event.

Work around

If using the RTCC alarm for Deep Sleep wake-up,

code should only enter Deep Sleep mode when

the RTCC Value Registers Read Synchronization

bit (RTCCFG<4>) is clear.

This will prevent missing an RTCC alarm that

could occur during the period after the SLEEP

instruction, but before the Deep Sleep mode has

been fully entered.

The A4 revision silicon allows insertion of a

single instruction between setting the Deep

Sleep Enable bit (DSEN, DSCONH<7>) and

issuing the SLEEP instruction (see Example 2).

The insertion of a NOP instruction before the

SLEEP instruction eliminates the 2 T

CY window

where wake-up events could be missed.

Before using this work around, users should

check their device’s revision ID bits to verify that

they have the A4 silicon. This can be done at run

time by a table read from address, 3FFFFEh.

On A2 revision silicon devices, the instruction

cannot be inserted between setting the DSEN

bit and executing the SLEEP instruction, or the

device will enter conventional Sleep mode, not

Deep Sleep.

On A4 silicon devices, if the firmware

immediately executes SLEEP after setting

DSEN, the device will enter Deep Sleep mode

without benefiting from this work around.

EXAMPLE 2: DEEP-SLEEP WAKE-UP WORK AROUND

Affected Silicon Revisions

EnterDeepSleep:

bsf DSCONH, DSEN ; Enter Deep Sleep mode on SLEEP instruction

nop ; Not compatible with A2 silicon

sleep ; Enter Deep Sleep mode

(…) ; Add code here to handle wake up events that may

; have been asserted prior to Deep Sleep entry

goto EnterDeepSleep ; re-attempt Deep Sleep entry if desired

A2 A4