Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 48 MHz I/O number 16

PIC18F46J11

DS80000435K-page 4  2009-2013 Microchip Technology Inc.

3. Module: Enhanced Universal

Synchronous Asynchronous

Receiver Transmitter (EUSART)

In rare situations when interrupts are enabled,

unexpected results may occur if:

• The EUSART is disabled (SPEN bit

(RCSTAx<7>) = 0)

• The EUSART is re-enabled

(RCSTAx<7> = 1)

• A two-cycle instruction is executed immediately

after setting SPEN, CREN or TXEN = 1

Work around

Add a 2 TCY delay after any instruction that

re-enables the EUSART module (sets SPEN,

CREN or TXEN = 1).

See Example 1.

Affected Silicon Revisions

EXAMPLE 1: RE-ENABLING AN EUSART MODULE

4. Module: 10-Bit Analog-to-Digital

Converter (A/D)

When the A/D conversion clock select bits are

set for F

OSC/2 (ADCON1<2:0> = 000), the

Integral Linearity Error (E

IL), parameter (A03)

and Differential Linearity Error (E

DL), parameter

(A04), may exceed data sheet specifications.

Work around

Select one of the alternate A/D clock sources

shown in Tab l e 3.

Affected Silicon Revisions

5. Module: Parallel Master Port (PMP)

When configured for Parallel Slave Port

(PMMODEH<1:0> = 00 and PMPEN = 1), the

data bus (PMD<7:0>) may not work correctly.

Incorrect data could be captured in the

PMDIN1L register.

When configured for Parallel Master Port

(PMMODEH<1:0> = 1x and PMPEN = 1),

clearing a PMEx bit to disable a PMP address

line also disables the corresponding PMDx data

bus line.

Work around

None.

Affected Silicon Revisions

A2 A4

;Initial conditions: SPEN = 0 (module disabled)

;To re-enable the module:

;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)

;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet

;Now enable the module, but add a 2-Tcy delay before executing any two-cycle

;instructions

bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2

nop ;1 Tcy delay

nop ;1 Tcy delay (two total)

;CPU may now execute 2 cycle instructions

TABLE 3: ALTERNATE ADC SETTINGS

ADCON1<2:0>

ADCS<2:0>

Clock Setting

110 F

OSC/64

101 F

OSC/16

100 FOSC/4

011 FRC

010 FOSC/32

001 FOSC/8

A2 A4