Information

 2009-2013 Microchip Technology Inc. DS80000435K-page 3
PIC18F46J11
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
In Master I
2
C™ Receive mode, if a Stop
condition occurs in the middle of an address or
data reception, the SCL clock stream will
continue endlessly and the RCEN bit of the
SSPCON2 register will remain improperly set.
When a Start condition occurs after the improper
Stop condition, nine additional clocks will be
generated, followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop
condition, and subsequently, the stuck RCEN
bit. Clear the stuck RCEN bit by clearing the
SSPEN bit of SSPCON1.
Affected Silicon Revisions
2. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C slave reception, the
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial Receive/Transmit Buffer Register
(SSPBUF) is not read after the SSPIF interrupt
(PIR1<3>) has occurred, but before the first rising
clock edge of the next byte being received.
Work around
The issue can be resolved in either of these
ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature. This is done by
setting the SEN bit (SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A2
A4
X
X
A2 A4
X
X