Information

© 2009 Microchip Technology Inc. DS80419B-page 1
PIC18F2480/2580/4480/4580
The PIC18F2480/2580/4480/4580 Rev. B0 parts you
have received conform functionally to the Device Data
Sheet (DS39637C), except for the anomalies
described below. Any Data Sheet Clarification issues
related to the PIC18F2480/2580/4480/4580 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All of the issues listed here will be addressed in future
revisions of the PIC18F2480/2580/4480/4580 silicon.
The following silicon errata apply only to
PIC18F2480/2580/4480/4580 devices with these
Device/Revision IDs:
1. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number Device ID Revision ID
PIC18F2480 0001 1010 100 0 0010
PIC18F2580 0001 1010 110 0 0010
PIC18F4480 0001 1010 101 0 0010
PIC18F4580 0001 1010 100 0 0010
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
PIC18F2480/2580/4480/4580 Rev. B0 Silicon Errata