Information

PIC18F2480/2580/4480/4580
DS80496C-page 4  2010 Microchip Technology Inc.
3. Module: ECCP
When operating either Timer1 or Timer3 as a
counter, with a prescale value other than 1:1 and
operating the ECCP in Compare mode with the
Special Event Trigger (CCP1CON bits,
CCP1M<3:0> = 1011), the Special Event
Trigger Reset of the timer occurs as soon as
there is a match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the
Special Event Trigger Reset of the timer occurs
on the next rollover of the prescale counter, after
the match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period as the
PIC18F458 devices, for a given clock source,
add 1 to the value in CCPR1H:CCPR1L. If
CCPR1H:CCPR1L = x for the PIC18F458,
achieve the same Reset period on a
PIC18F2480/2580/4480/4580 device by using
CCPR1H:CCPR1L = x + 1, where the prescale is
1, 2, 4 or 8 (depending on the T1CKPS<1:0> bit
values).
Affected Silicon Revisions
4. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXIF. This is because any write to the
TXSTA register results in a Reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by poll-
ing TXIF or by writing TX9D at the beginning of
the Interrupt Service Routine. Alternately, only
write to TX9D when a transmission is not in
progress (TRMT = 1).
Affected Silicon Revisions
5. Module: Timer1/3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen
the duration of the period between the incre-
ments of the timer for the period in which
TMR1H/TMR3H were written. It does not
change the actual prescale value.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/
TMR3L immediately following a write to
TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait
for another event before also updating
TMR1L/TMR3L.
Affected Silicon Revisions
A1 B0 B2
X
A1 B0 B2
X
A1 B0 B2
X