Information

 2010 Microchip Technology Inc. DS80496C-page 3
PIC18F2480/2580/4480/4580
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C slave reception, the
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial Receive/Transmit Buffer register
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next
byte being received.
Affected Silicon Revisions
2. Module: Brown-out Reset (BOR)
The BOR module may reset above the
parameter D005 value specified in Section 28.1
“DC Characteristics: Supply Voltage” when:
•BORV<1:0> = 01 or 00
•FOSC is above 26 MHz
The updated BOR voltage specifications are
shown in the Section 28.1 table.
Work around
To address this situation:
• Reduce F
OSC to 25 MHz
• Use the lower of the two affected BOR
voltage thresholds, BORV<1:0>
(CONFIG2L<4:3>) = 01
This will ensure detection of V
DD below 5.0V.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B2).
A1 B0 B2
XX
X
28.1 DC Characteristics: Supply Voltage
PIC18F2480/2580/4480/4580 (Industrial, Extended)
PIC18LF2480/2580/4480/4580 (Industrial)
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
D005 V
BOR Brown-out Reset Voltage
BORV<1:0> = 01 4.47 4.69 4.91 V F
OSC > 26 MHz
BORV<1:0> = 00 4.72 4.95 5.18 V F
OSC > 26 MHz
A1 B0 B2
X