Information

PIC18F2480/2580/4480/4580
DS80496C-page 2  2010 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A1 B0 B2
MSSP I
2
C™ 1.
Slave reception receives incorrect data if not
read at the correct time.
XXX
BOR Trip Level 2. Trip levels are off at high frequencies. X
ECCP
Special Event
Trigger
3.
The Special Event Trigger Reset does not occur
on the next rollover of the prescaler counter.
X
EUSART Transmission 4.
Nine-bit timing can be corrupted if the TX9D bit
is not written immediately after TXIF is set.
X
Timer1/3 16-Bit Mode 5.
The TMR1H/TMR3H Buffer registers may
lengthen the duration of the period between the
increments of the timer.
X
Interrupts
Two-Cycle
Instruction
6.
If an interrupt occurs during a two-cycle
instruction modifying the STATUS, BSR or
WREG register, the previous value is saved to
the Fast Return register.
X
ECAN™
Technology
Transmit
Buffer ID
7.
The first five bits of a transmitted identifier may
not match the transmit buffer ID.
X
ECAN
Technology
Error
Interruption
Flag
8.
The error interrupt flag may not be able to be
cleared in software if the TXERRCNT or
RXERRCNT counters exceed 127.
X
ECAN
Technology
Configuration
Mode
9.
After an error on the bus, the module is unable
to switch directly from Listen Only mode to
Configuration mode.
X
ECAN
Technology
TXBnSIDH
Register
10. May become corrupted. X
ECAN
Technology
Listen Only
Mode
11.
IRXIF, RXB0IF and RXFUL flags are
consistently set after 129 or more consistent
error frames.
X
10-Bit ADC E
IL and EDL 12.
E
IL and EDL may exceed data sheet
specifications at codes, 511 and 512.
X
MSSP SPI 13.
SDO output may change after inactive lock
edge of Bit 0.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.