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 2010 Microchip Technology Inc. DS80496C-page 1

PIC18F2480/2580/4480/4580

The PIC18F2480/2580/4480/4580 devices that you

have received conform functionally to the current Device

Data Sheet (DS39637D), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be

addressed in future revisions of the PIC18F2480/2580/

4480/4580 silicon.

Data Sheet clarifications and corrections start on

page 11, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select Con-

figure>Select Device, and then select the target

part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC18F2480/2580/

4480/4580 silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revision

(B2).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A1 B0 B2

PIC18F2480 1AEh

1h 2h 4h

PIC18F2580 1ACh

PIC18F4480 1AAh

PIC18F4580 1A8h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC18F2XXX/4XXXX Family Flash Microcontroller Programming Specification” (DS39622)

for detailed information on Device and Revision IDs for your specific device.

PIC18F2480/2580/4480/4580

Silicon Errata and Data Sheet Clarification

Summary of content (14 pages)

PAGE 1
PIC18F2480/2580/4480/4580 PIC18F2480/2580/4480/4580 Silicon Errata and Data Sheet Clarification The PIC18F2480/2580/4480/4580 devices that you have received conform functionally to the current Device Data Sheet (DS39637D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC18F2480/2580/4480/4580 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A1 B0 B2 X X X MSSP I2C™ 1. Slave reception receives incorrect data if not read at the correct time. BOR Trip Level 2. Trip levels are off at high frequencies. ECCP Special Event Trigger 3. The Special Event Trigger Reset does not occur on the next rollover of the prescaler counter. X EUSART Transmission 4.
PAGE 3
PIC18F2480/2580/4480/4580 Silicon Errata Issues Note: Work around The issue can be resolved in either of these ways: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B2). • Prior to the I2C slave reception, enable the clock stretching feature. This is done by (SSPCON2<0>).
PAGE 4
PIC18F2480/2580/4480/4580 3. Module: ECCP When operating either Timer1 or Timer3 as a counter, with a prescale value other than 1:1 and operating the ECCP in Compare mode with the Special Event Trigger (CCP1CON bits, CCP1M<3:0> = 1011), the Special Event Trigger Reset of the timer occurs as soon as there is a match between TMRxH:TMRxL and CCPR1H:CCPR1L.
PAGE 5
PIC18F2480/2580/4480/4580 6. Module: Interrupts Work around If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register. Upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register.
PAGE 6
PIC18F2480/2580/4480/4580 2. C Language Programming: The exact work around depends on the compiler in use. Consult the C compiler’s documentation for details. If using the Microchip MPLAB® C18 C Compiler, define both high and low-priority interrupt handler functions as “low priority” by using the pragma interruptlow directive. This directive instructs the compiler to not use EXAMPLE 2: the RETFIE FAST instruction.
PAGE 7
PIC18F2480/2580/4480/4580 An optimized C18 version, illustrating how to reduce the instruction cycle count to three, is provided in Example 3. Affected Silicon Revisions A1 B0 B2 X EXAMPLE 3: OPTIMIZED INTERRUPT SERVICE ROUTINE #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr void high_isr (void) { ... }  2010 Microchip Technology Inc.
PAGE 8
PIC18F2480/2580/4480/4580 7. Module: ECAN™ Technology Under specific conditions, the first five bits of a transmitted identifier may not match the value in the Transmit Buffer ID register, TXBnSIDH. The following conditions must exist for the corruption to occur: • A transmit message must be pending • The ECAN module must detect a Start-of-Frame (SOF) in the third bit of the interframe space.
PAGE 9
PIC18F2480/2580/4480/4580 10. Module: ECAN Technology Work around Under specific conditions, the TXBnSIDH register of the pending message for transmission may be corrupted. This occurs when the following conditions exist: Ensure that a receive buffer overflow condition does not occur and/or ensure that a transmit request is not pending if a receive buffer overflow condition does exist. • A transmit message is pending.
PAGE 10
PIC18F2480/2580/4480/4580 11. Module: ECAN Technology 13. Module: MSSP In Listen Only mode, the module may persistently set the IRXIF and RXB0IF interrupt flags, and the RXFUL status flag, after receiving 129 or more consecutive error frames. In this case, the flags can be cleared, but then will become set again immediately and continuously without receiving a bus message. In SPI mode, the SDO output may change after the inactive clock edge of the Bit 0 output.
PAGE 11
PIC18F2480/2580/4480/4580 Data Sheet Clarifications APPENDIX A: The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39637D): Rev A Document (2/2010) Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. DOCUMENT REVISION HISTORY Original release of this errata, combining previous errata for silicon revisions, A1 and B0, and superseding the data sheet errata.
PAGE 12
PIC18F2480/2580/4480/4580 NOTES: DS80496C-page 12  2010 Microchip Technology Inc.
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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