Information

PIC18F2458/2553/4458/4553
DS80387A-page 2 © 2008 Microchip Technology Inc.
2. Module: MSSP
With MSSP in SPI Master mode, FOSC/64 or
Timer2/2 clock rate and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• A non-zero dead-band delay is specified
(PDC6:PDC0 > 0)
• The duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1)
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Electrical Characteristics (BOR)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the device data sheet (parameter D005).
The BOR threshold has been observed to increase
with some table read operations. BOR has been
observed with 7 percent higher V
DD than the VBOR
value specified for a given BORV<1:0> setting.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.