Information

PIC18F2450/4450

2. Module: USB

In Section 14.4.3 “BD Address Validation”, the

USB RAM address range described in the first

paragraph is 400h to 7FFh. The correct range is

400h to 4FFh.

3. Module: USB

In Register 14-5 (BDnSTAT, CPU Mode), the

operation of the DSTEN bit is clarified with

additional text, shown below in bold.

4. Module: USB

In Section 14.5 “USB Interrupts”, the following

subsection is inserted immediately after

Section 14.5.1 “USB Interrupt Status Register

(UIR)”:

14.5.1.1 Bus Activity Detect Interrupt Bit

(ACTVIF)

The ACTVIF bit cannot be cleared immediately after

the USB module wakes up from Suspend or while the

USB module is suspended. A few clock cycles are

required to synchronize the internal hardware state

machine before the ACTVIF bit can be cleared by

firmware. Clearing the ACTVIF bit before the internal

hardware is synchronized may not have an effect on

the value of ACTVIF. Additionally, if the USB module

uses the clock from the 96 MHz PLL source, then after

clearing the SUSPND bit, the USB module may not be

immediately operational while waiting for the 96 MHz

PLL to lock. The application code should clear the

ACTVIF bit as shown in Example 14-1.

EXAMPLE 14-1: CLEARING ACTVIF BIT (UIR<2>)

BD63STAT), CPU MODE (PARTIAL REPRESENTATION)

bit 3 DTSEN: Data Toggle Synchronization Enable bit

1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored

except for a SETUP transaction, which is accepted even if the data toggle bits do not

match

0 = No data toggle synchronization is performed

Assembly:

BCF UCON, SUSPND

LOOP:

BTFSS UIR, ACTVIF

BRA DONE

BCF UIR, ACTVIF

BRA LOOP

DONE

UCONbits.SUSPND = 0;

while (UIRbits.ACTVIF){UIRbits.ACTVIF = 0};