Information

© 2007 Microchip Technology Inc. DS80309B-page 1
PIC18F2450/4450
The PIC18F2450/4450 parts you have received
conform functionally to the Device Data Sheet
(DS39760B), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F2450/4450 devices will be reported in a
separate Data Sheet errata. Please check the
Microchip web site for any existing issues.
The following silicon errata apply only to
PIC18F2450/4450 devices with these Device/
Revision IDs:
All of the issues listed here will be addressed in future
revisions of the PIC18F2450/4450 silicon.
1. Module: EUSART
In Synchronous Master mode, while transmitting
the Most Significant data bit, the data line (DT)
may change state before the bit finishes transmit-
ting. If the receiver samples the data line later than
0.5 bit times + 1.5 TCY (of the master) after the
starting edge of the MSb, the bit may be read
incorrectly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
2. Module: 10-Bit Analog-to-Digital (A/D)
Converter Module
When the A/D clock source is selected as 2 TOSC
or RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
IL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 TOSC,
8T
OSC, 16 TOSC, 32 TOSC or 64 TOSC) and avoid
selecting the 2 T
OSC or RC modes.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number Device ID Revision ID
PIC18F2450 0001 0100 001 0 0010
PIC18F4450 0001 0100 000 0 0010
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
PIC18F2450/4450 Rev. A3 Silicon Errata