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PIC18F2450/4450

The PIC18F2450/4450 (Rev. A1) parts you have

received conform functionally to the Device Data Sheet

(DS39760A), except for the anomalies described

below. Any data sheet clarification issues related to this

device will be reported in a separate data sheet errata.

Please check the Microchip web site for any existing

issues.

The following silicon errata apply only to

PIC18F2450/4450 devices with these Device/Revision

IDs:

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s configu-

ration space. They are shown in hexadecimal in the

format “DEVID2 DEVID1”.

1. Module: EUSART

In Asynchronous mode, the reception can get

corrupted if any bit of the TXSTA register is

modified during a reception.

Work around

Maintain CSRC (TXSTA<7>) and SYNC

(TXSTA<4>) bits as ‘0’. Though the CSRC

(TXSTA<7>) bit is a don’t care in Asynchronous

mode, make sure that this bit is not set.

2. Module: A/D (Offset)

The A/D offset is greater than the specified limit in

Table 21-17 of the Device Data Sheet. The

updated conditions and limits are shown in bold

text in Table 1.

Work around

There are three work arounds:

1. Configure the A/D to use the V

REF+ and VREF-

pins for the voltage references. This is done by

setting the VCFG<1:0> bits (ADCON1<5:4>).

2. Perform a conversion on a known voltage

reference voltage and adjust the A/D result in

software.

3. Increase system clock speed and adjust A/D

settings accordingly. Higher system clock

frequencies decrease offset error.

TABLE 1: A/D CONVERTER CHARACTERISTICS (PIC18F2450/4450)

Part Number Device ID Revision ID

PIC18F2450 01 0100 001 00001

PIC18F4450 01 0100 000 00001

Param

No.

Symbol Characteristic Min Typ Max Units Conditions

A06A E

OFF Offset Error ——<±1.5 LSb VREF = VREF+ and VREF-

A06 E

OFF Offset Error — — <±3.5 LSb VREF = VSS and VDD

PIC18F2450/4450 Rev. A1 Silicon Errata

Summary of content (6 pages)

PAGE 1
PIC18F2450/4450 PIC18F2450/4450 Rev. A1 Silicon Errata 2. Module: A/D (Offset) The PIC18F2450/4450 (Rev. A1) parts you have received conform functionally to the Device Data Sheet (DS39760A), except for the anomalies described below. Any data sheet clarification issues related to this device will be reported in a separate data sheet errata. Please check the Microchip web site for any existing issues. The A/D offset is greater than the specified limit in Table 21-17 of the Device Data Sheet.
PAGE 2
PIC18F2450/4450 3. Module: A/D (Channels) In Section 16.0 “10-Bit Analog-to-Digital Converter (A/D) Module” of the Device Data Sheet, it mentions the Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. Actually, the PIC18F2450 (28-pin) devices have only 7 channels available instead of 10. The ADC channels, AN10, AN11 and AN12 (RB1, RB4, RB0 pins, respectively) are not available. DS80266A-page 2 4.
PAGE 3
PIC18F2450/4450 REVISION HISTORY Rev A Document (03/2006) Original version of this document. Includes silicon issues 1 (EUSART), 2 (A/D – Offset), 3 (A/D – Channels) and 4 (DC Characteristics – BOR). © 2006 Microchip Technology Inc.
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
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