Information

PIC18F2423/2523/4423/4523
DS80289E-page 2 © 2007 Microchip Technology Inc.
2. Module: MSSP
With MSSP in SPI Master mode, FOSC/64 or
Timer2/2 clock rate, and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur, as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: Timer1 and Timer3
For Timer1 or Timer3, if the TMRxH and TMRxL
registers are written to in consecutive instruction
cycles, the timer may not be updated with the
correct value when configured for externally
clocked 8-Bit Asynchronous mode (T1CON<7:0>
or T3CON<7:0> = 0xxx x111).
Work around
Insert a delay of one or more instruction cycles
between writes to TMRxH and TMRxL. This delay
can be a NOP, or any instruction that does not
access the Timer registers (Example 1).
EXAMPLE 1:
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM out-
put may be corrupted for certain values of the
PWM duty cycle. This occurs when these
additional criteria are also met:
• a non-zero, dead-band delay is specified
(PDC6:PDC0 > 0); and
• the duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
CLRF TMR1H
MOVLW T1Offset ; 1 Tcy delay
MOVWF TMR1L
Note: The ECCP module is implemented only in
40/44-pin devices.