Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39631B-page 383
PIC18F2420/2520/4420/4520
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 197
Brown-out Reset (BOR) ...........................................345
Bus Collision During a Repeated
Start Condition (Case 1) ..................................198
Bus Collision During a Repeated
Start Condition (Case 2) ..................................198
Bus Collision During a Start Condition
(SCL = 0) .........................................................197
Bus Collision During a Stop Condition
(Case 1) ...........................................................199
Bus Collision During a Stop Condition
(Case 2) ...........................................................199
Bus Collision During Start Condition
(SDA only) .......................................................196
Bus Collision for Transmit and Acknowledge ........... 195
Capture/Compare/PWM (CCP) ................................ 347
CLKO and I/O .......................................................... 344
Clock Synchronization ............................................. 181
Clock/Instruction Cycle ..............................................57
Example SPI Master Mode (CKE = 0) ..................... 349
Example SPI Master Mode (CKE = 1) ..................... 350
Example SPI Slave Mode (CKE = 0) .......................351
Example SPI Slave Mode (CKE = 1) .......................352
External Clock (All Modes except PLL) .................... 342
Fail-Safe Clock Monitor (FSCM) .............................. 262
First Start Bit Timing ................................................189
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output .........................................152
High/Low-Voltage Detect Characteristics ................ 339
High/Low-Voltage Detect Operation
(VDIRMAG = 0) ................................................245
High/Low-Voltage Detect Operation
(VDIRMAG = 1) ................................................246
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2
C Bus Data ............................................................353
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2
C Bus Start/Stop Bits .............................................353
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2
C Master Mode (7 or 10-Bit Transmission) ........... 192
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2
C Master Mode (7-Bit Reception) .......................... 193
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 178
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 183
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2
C Slave Mode (10-Bit Transmission) ..................... 179
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2
C Slave Mode (7-bit Reception, SEN = 0) .............176
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2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 182
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2
C Slave Mode (7-Bit Transmission) ....................... 177
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2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 184
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2
C Stop Condition Receive or
Transmit Mode ................................................. 194
Master SSP I
2
C Bus Data ........................................ 355
Master SSP I
2
C Bus Start/Stop Bits ........................ 355
Parallel Slave Port (PIC18F4420/4520) ................... 348
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ....................................158
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 158
PWM Direction Change ........................................... 155
PWM Direction Change at Near
100% Duty Cycle .............................................155
PWM Output ............................................................ 144
Repeat Start Condition ............................................ 190
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 345
Send Break Character Sequence ............................ 216
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception
(Master Mode, SREN) ..................................... 219
Synchronous Transmission ..................................... 217
Synchronous Transmission (Through TXEN) .......... 218
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) .......................................... 47
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 1) ...................... 46
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 2) ...................... 46
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 346
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 260
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition Timing for Entry to Idle Mode .................... 38
Transition Timing for Wake from
Idle to Run Mode ............................................... 38
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
(Master/Slave) ................................................. 357
USART Synchronous Transmission
(Master/Slave) ................................................. 357
Timing Diagrams and Specifications ............................... 342
A/D Conversion Requirements ................................ 359
Capture/Compare/PWM Requirements ................... 347
CLKO and I/O Requirements ................................... 344
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 349
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 350
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 351
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 352
External Clock Requirements .................................. 342
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2
C Bus Data Requirements (Slave Mode) .............. 354
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2
C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 353
Master SSP I
2
C Bus Data Requirements ................ 356
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 355
Parallel Slave Port Requirements
(PIC18F4420/4520) ......................................... 348