Datasheet

PIC18F2420/2520/4420/4520
DS39631B-page 350 Preliminary © 2007 Microchip Technology Inc.
FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 26-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
71 TscH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode)
Continuous 1.25 T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 T
CY + 40 — ns (Note 2)
74 TscH2diL,
TscL 2d iL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns V
DD = 2.0V
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Time
(Master mode)
PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns V
DD = 2.0V
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after
SCK Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX 100 ns V
DD = 2.0V
81 TdoV2scH,
TdoV2scL
SDO Data Output Setup to SCK Edge TCY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.