Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39631B-page 345
PIC18F2420/2520/4420/4520
FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 26-8: BROWN-OUT RESET TIMING
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
—4.00TBD ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period — 65.5 TBD ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—μs
35 T
BOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005)
36 T
IVRST Time for Internal Reference
Voltage to become Stable
—2050 μs
37 T
LVD High/Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD
38 TCSD CPU Start-up Time 5 — 10 μs
39 TIOBST Time for INTOSC to Stabilize — 1 — ms
Legend: TBD = To Be Determined
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 26-4 for load conditions.
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable