Datasheet

PIC18F2420/2520/4420/4520
DS39631B-page 224 Preliminary © 2007 Microchip Technology Inc.
REGISTER 19-2: ADCON1 REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0
(1)
R/W
(1)
R/W
(1)
R/W
(1)
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (V
REF- source)
1 = V
REF- (AN2)
0 = V
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = V
DD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
A = Analog input D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN con
-
figuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0
,
PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
PCFG3:
PCFG0
AN12 AN11 AN10 AN9 AN8 AN7
(2
)
AN6
(2
)
AN5
(2
)
AN4 AN3 AN2 AN1 AN0
0000
(1)
AAAAAAAAAAAAA
0001 A AAAAAAAAAAAA
0010 A AAAAAAAAAAAA
0011 DAAAAAAAAAAAA
0100 DDAAAAAAAAAAA
0101 DDDAAAAAAAAAA
0110 DDDDAAAAAAAAA
0111
(1)
DDDDDAAAAAAAA
1000 DDDDDDAAAAAAA
1001 DDDDDDDAAAAAA
1010 DDDDDDDDAAAAA
1011 DDDDDDDDDAAAA
1100 DDDDDDDDDDAAA
1101 DDDDDDDDDDDAA
1110 DDDDDDDDDDDDA
1111 DDDDDDDDDDDDD